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Daniele Ceraolo Spurio 484ecffac9 drm/xe/huc: Extract version and binary offset from new HuC headers
The GSC-enabled HuC binary starts with a GSC header, which is followed
by the legacy-style CSS header and the binary itself. We can parse the
GSC headers to find the HuC version and the location of the binary to
be used for the DMA transfer.

The parsing function has been designed to be re-used for the GSC binary,
so the entry names are external parameters (because the GSC uses
different ones) and the CSS entry is optional (because the GSC doesn't
have it).

v2: move new code to uc_fw.c, better comments and error checking, split
    old code move to separate patch (Lucas), move headers and
    documentation to uc_fw_abi.h.

v3: use 2 separate loops, rework marker check (Lucas)

Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Alan Previn <alan.previn.teres.alexis@intel.com>
Cc: John Harrison <John.C.Harrison@Intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2023-12-21 11:43:22 -05:00
..
amdgpu
bridge
dp-mst
imagination
rfc
xe drm/xe/huc: Extract version and binary offset from new HuC headers 2023-12-21 11:43:22 -05:00
afbc.rst
automated_testing.rst
backlight.rst
driver-uapi.rst drm/doc: include xe_drm.h 2023-12-21 11:35:00 -05:00
drivers.rst drm/xe: Introduce a new DRM driver for Intel GPUs 2023-12-12 14:05:48 -05:00
drm-client.rst
drm-internals.rst
drm-kms-helpers.rst
drm-kms.rst
drm-mm.rst
drm-uapi.rst
drm-usage-stats.rst
drm-vm-bind-async.rst
drm-vm-bind-locking.rst
i915.rst
implementation_guidelines.rst
index.rst
introduction.rst
kms-properties.csv
komeda-kms.rst
mcde.rst
meson.rst
msm-crash-dump.rst
panfrost.rst
pl111.rst
tegra.rst
todo.rst
tve200.rst
v3d.rst
vc4.rst
vga-switcheroo.rst
vgaarbiter.rst
vkms.rst
xen-front.rst