8cda7a4f96
Add a new CTX ioctl operation to set stable pstates for profiling. When creating traces for tools like RGP or using SPM or doing performance profiling, it's required to enable a special stable profiling power state on the GPU. These profiling states set fixed clocks and disable certain other power features like powergating which may impact the results. Historically, these profiling pstates were enabled via sysfs, but this adds an interface to enable it via the CTX ioctl from the application. Since the power state is global only one application can set it at a time, so if multiple applications try and use it only the first will get it, the ioctl will return -EBUSY for others. The sysfs interface will override whatever has been set by this interface. Mesa MR: https://gitlab.freedesktop.org/mesa/drm/-/merge_requests/207 v2: don't default r = 0; v3: rebase on Evan's PM cleanup Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
94 lines
3.3 KiB
C
94 lines
3.3 KiB
C
/*
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* Copyright 2018 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __AMDGPU_CTX_H__
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#define __AMDGPU_CTX_H__
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#include "amdgpu_ring.h"
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struct drm_device;
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struct drm_file;
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struct amdgpu_fpriv;
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#define AMDGPU_MAX_ENTITY_NUM 4
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#define AMDGPU_CTX_FENCE_USAGE_MIN_RATIO(max, total) ((max) > 16384ULL*(total))
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struct amdgpu_ctx_entity {
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uint64_t sequence;
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struct drm_sched_entity entity;
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struct dma_fence *fences[];
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};
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struct amdgpu_ctx {
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struct kref refcount;
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struct amdgpu_device *adev;
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unsigned reset_counter;
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unsigned reset_counter_query;
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uint32_t vram_lost_counter;
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spinlock_t ring_lock;
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struct amdgpu_ctx_entity *entities[AMDGPU_HW_IP_NUM][AMDGPU_MAX_ENTITY_NUM];
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bool preamble_presented;
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int32_t init_priority;
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int32_t override_priority;
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struct mutex lock;
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atomic_t guilty;
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unsigned long ras_counter_ce;
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unsigned long ras_counter_ue;
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uint32_t stable_pstate;
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};
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struct amdgpu_ctx_mgr {
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struct amdgpu_device *adev;
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struct mutex lock;
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/* protected by lock */
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struct idr ctx_handles;
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};
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extern const unsigned int amdgpu_ctx_num_entities[AMDGPU_HW_IP_NUM];
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struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
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int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
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int amdgpu_ctx_get_entity(struct amdgpu_ctx *ctx, u32 hw_ip, u32 instance,
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u32 ring, struct drm_sched_entity **entity);
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void amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx,
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struct drm_sched_entity *entity,
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struct dma_fence *fence, uint64_t *seq);
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struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
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struct drm_sched_entity *entity,
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uint64_t seq);
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bool amdgpu_ctx_priority_is_valid(int32_t ctx_prio);
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void amdgpu_ctx_priority_override(struct amdgpu_ctx *ctx, int32_t ctx_prio);
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int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
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struct drm_file *filp);
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int amdgpu_ctx_wait_prev_fence(struct amdgpu_ctx *ctx,
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struct drm_sched_entity *entity);
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void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
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void amdgpu_ctx_mgr_entity_fini(struct amdgpu_ctx_mgr *mgr);
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long amdgpu_ctx_mgr_entity_flush(struct amdgpu_ctx_mgr *mgr, long timeout);
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void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
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ktime_t amdgpu_ctx_mgr_fence_usage(struct amdgpu_ctx_mgr *mgr, uint32_t hwip,
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uint32_t idx, uint64_t *elapsed);
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#endif
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