920c293af8
This adds the interrupt for the Sparx5 Frame DMA. If this configuration is present the Sparx5 SwitchDev driver will use the Frame DMA feature, and if not it will use register based injection and extraction for sending and receiving frames to the CPU. Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
481 lines
11 KiB
Text
481 lines
11 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
|
/*
|
|
* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
|
|
*/
|
|
|
|
#include <dt-bindings/gpio/gpio.h>
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
#include <dt-bindings/clock/microchip,sparx5.h>
|
|
|
|
/ {
|
|
compatible = "microchip,sparx5";
|
|
interrupt-parent = <&gic>;
|
|
#address-cells = <2>;
|
|
#size-cells = <1>;
|
|
|
|
aliases {
|
|
spi0 = &spi0;
|
|
serial0 = &uart0;
|
|
serial1 = &uart1;
|
|
};
|
|
|
|
chosen {
|
|
stdout-path = "serial0:115200n8";
|
|
};
|
|
|
|
cpus {
|
|
#address-cells = <2>;
|
|
#size-cells = <0>;
|
|
cpu-map {
|
|
cluster0 {
|
|
core0 {
|
|
cpu = <&cpu0>;
|
|
};
|
|
core1 {
|
|
cpu = <&cpu1>;
|
|
};
|
|
};
|
|
};
|
|
cpu0: cpu@0 {
|
|
compatible = "arm,cortex-a53";
|
|
device_type = "cpu";
|
|
reg = <0x0 0x0>;
|
|
enable-method = "psci";
|
|
next-level-cache = <&L2_0>;
|
|
};
|
|
cpu1: cpu@1 {
|
|
compatible = "arm,cortex-a53";
|
|
device_type = "cpu";
|
|
reg = <0x0 0x1>;
|
|
enable-method = "psci";
|
|
next-level-cache = <&L2_0>;
|
|
};
|
|
L2_0: l2-cache0 {
|
|
compatible = "cache";
|
|
};
|
|
};
|
|
|
|
arm-pmu {
|
|
compatible = "arm,cortex-a53-pmu";
|
|
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-affinity = <&cpu0>, <&cpu1>;
|
|
};
|
|
|
|
psci {
|
|
compatible = "arm,psci-0.2";
|
|
method = "smc";
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
|
|
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
|
|
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
|
|
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
lcpll_clk: lcpll-clk {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <2500000000>;
|
|
};
|
|
|
|
clks: clock-controller@61110000c {
|
|
compatible = "microchip,sparx5-dpll";
|
|
#clock-cells = <1>;
|
|
clocks = <&lcpll_clk>;
|
|
reg = <0x6 0x1110000c 0x24>;
|
|
};
|
|
|
|
ahb_clk: ahb-clk {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <250000000>;
|
|
};
|
|
|
|
sys_clk: sys-clk {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <625000000>;
|
|
};
|
|
|
|
axi: axi@600000000 {
|
|
compatible = "simple-bus";
|
|
#address-cells = <2>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
gic: interrupt-controller@600300000 {
|
|
compatible = "arm,gic-v3";
|
|
#interrupt-cells = <3>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
interrupt-controller;
|
|
reg = <0x6 0x00300000 0x10000>, /* GIC Dist */
|
|
<0x6 0x00340000 0xc0000>, /* GICR */
|
|
<0x6 0x00200000 0x2000>, /* GICC */
|
|
<0x6 0x00210000 0x2000>, /* GICV */
|
|
<0x6 0x00220000 0x2000>; /* GICH */
|
|
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
cpu_ctrl: syscon@600000000 {
|
|
compatible = "microchip,sparx5-cpu-syscon", "syscon",
|
|
"simple-mfd";
|
|
reg = <0x6 0x00000000 0xd0>;
|
|
mux: mux-controller {
|
|
compatible = "mmio-mux";
|
|
#mux-control-cells = <0>;
|
|
/*
|
|
* SI_OWNER and SI2_OWNER in GENERAL_CTRL
|
|
* SPI: value 9 - (SIMC,SIBM) = 0b1001
|
|
* SPI2: value 6 - (SIBM,SIMC) = 0b0110
|
|
*/
|
|
mux-reg-masks = <0x88 0xf0>;
|
|
};
|
|
};
|
|
|
|
reset: reset-controller@611010008 {
|
|
compatible = "microchip,sparx5-switch-reset";
|
|
reg = <0x6 0x11010008 0x4>;
|
|
reg-names = "gcb";
|
|
#reset-cells = <1>;
|
|
cpu-syscon = <&cpu_ctrl>;
|
|
};
|
|
|
|
uart0: serial@600100000 {
|
|
pinctrl-0 = <&uart_pins>;
|
|
pinctrl-names = "default";
|
|
compatible = "ns16550a";
|
|
reg = <0x6 0x00100000 0x20>;
|
|
clocks = <&ahb_clk>;
|
|
reg-io-width = <4>;
|
|
reg-shift = <2>;
|
|
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
uart1: serial@600102000 {
|
|
pinctrl-0 = <&uart2_pins>;
|
|
pinctrl-names = "default";
|
|
compatible = "ns16550a";
|
|
reg = <0x6 0x00102000 0x20>;
|
|
clocks = <&ahb_clk>;
|
|
reg-io-width = <4>;
|
|
reg-shift = <2>;
|
|
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
spi0: spi@600104000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "microchip,sparx5-spi";
|
|
reg = <0x6 0x00104000 0x40>;
|
|
num-cs = <16>;
|
|
reg-io-width = <4>;
|
|
reg-shift = <2>;
|
|
clocks = <&ahb_clk>;
|
|
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
timer1: timer@600105000 {
|
|
compatible = "snps,dw-apb-timer";
|
|
reg = <0x6 0x00105000 0x1000>;
|
|
clocks = <&ahb_clk>;
|
|
clock-names = "timer";
|
|
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
sdhci0: mmc@600800000 {
|
|
compatible = "microchip,dw-sparx5-sdhci";
|
|
status = "disabled";
|
|
reg = <0x6 0x00800000 0x1000>;
|
|
pinctrl-0 = <&emmc_pins>;
|
|
pinctrl-names = "default";
|
|
clocks = <&clks CLK_ID_AUX1>;
|
|
clock-names = "core";
|
|
assigned-clocks = <&clks CLK_ID_AUX1>;
|
|
assigned-clock-rates = <800000000>;
|
|
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
|
bus-width = <8>;
|
|
};
|
|
|
|
gpio: pinctrl@6110101e0 {
|
|
compatible = "microchip,sparx5-pinctrl";
|
|
reg = <0x6 0x110101e0 0x90>, <0x6 0x10508010 0x100>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
gpio-ranges = <&gpio 0 0 64>;
|
|
interrupt-controller;
|
|
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
|
#interrupt-cells = <2>;
|
|
|
|
cs1_pins: cs1-pins {
|
|
pins = "GPIO_16";
|
|
function = "si";
|
|
};
|
|
|
|
cs2_pins: cs2-pins {
|
|
pins = "GPIO_17";
|
|
function = "si";
|
|
};
|
|
|
|
cs3_pins: cs3-pins {
|
|
pins = "GPIO_18";
|
|
function = "si";
|
|
};
|
|
|
|
si2_pins: si2-pins {
|
|
pins = "GPIO_39", "GPIO_40", "GPIO_41";
|
|
function = "si2";
|
|
};
|
|
|
|
sgpio0_pins: sgpio-pins {
|
|
pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3";
|
|
function = "sg0";
|
|
};
|
|
|
|
sgpio1_pins: sgpio1-pins {
|
|
pins = "GPIO_4", "GPIO_5", "GPIO_12", "GPIO_13";
|
|
function = "sg1";
|
|
};
|
|
|
|
sgpio2_pins: sgpio2-pins {
|
|
pins = "GPIO_30", "GPIO_31", "GPIO_32",
|
|
"GPIO_33";
|
|
function = "sg2";
|
|
};
|
|
|
|
uart_pins: uart-pins {
|
|
pins = "GPIO_10", "GPIO_11";
|
|
function = "uart";
|
|
};
|
|
|
|
uart2_pins: uart2-pins {
|
|
pins = "GPIO_26", "GPIO_27";
|
|
function = "uart2";
|
|
};
|
|
|
|
i2c_pins: i2c-pins {
|
|
pins = "GPIO_14", "GPIO_15";
|
|
function = "twi";
|
|
};
|
|
|
|
i2c2_pins: i2c2-pins {
|
|
pins = "GPIO_28", "GPIO_29";
|
|
function = "twi2";
|
|
};
|
|
|
|
emmc_pins: emmc-pins {
|
|
pins = "GPIO_34", "GPIO_35", "GPIO_36",
|
|
"GPIO_37", "GPIO_38", "GPIO_39",
|
|
"GPIO_40", "GPIO_41", "GPIO_42",
|
|
"GPIO_43", "GPIO_44", "GPIO_45",
|
|
"GPIO_46", "GPIO_47";
|
|
function = "emmc";
|
|
};
|
|
|
|
miim1_pins: miim1-pins {
|
|
pins = "GPIO_56", "GPIO_57";
|
|
function = "miim";
|
|
};
|
|
|
|
miim2_pins: miim2-pins {
|
|
pins = "GPIO_58", "GPIO_59";
|
|
function = "miim";
|
|
};
|
|
|
|
miim3_pins: miim3-pins {
|
|
pins = "GPIO_52", "GPIO_53";
|
|
function = "miim";
|
|
};
|
|
};
|
|
|
|
sgpio0: gpio@61101036c {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "microchip,sparx5-sgpio";
|
|
status = "disabled";
|
|
clocks = <&sys_clk>;
|
|
pinctrl-0 = <&sgpio0_pins>;
|
|
pinctrl-names = "default";
|
|
resets = <&reset 0>;
|
|
reset-names = "switch";
|
|
reg = <0x6 0x1101036c 0x100>;
|
|
sgpio_in0: gpio@0 {
|
|
compatible = "microchip,sparx5-sgpio-bank";
|
|
reg = <0>;
|
|
gpio-controller;
|
|
#gpio-cells = <3>;
|
|
ngpios = <96>;
|
|
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
};
|
|
sgpio_out0: gpio@1 {
|
|
compatible = "microchip,sparx5-sgpio-bank";
|
|
reg = <1>;
|
|
gpio-controller;
|
|
#gpio-cells = <3>;
|
|
ngpios = <96>;
|
|
};
|
|
};
|
|
|
|
sgpio1: gpio@611010484 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "microchip,sparx5-sgpio";
|
|
status = "disabled";
|
|
clocks = <&sys_clk>;
|
|
pinctrl-0 = <&sgpio1_pins>;
|
|
pinctrl-names = "default";
|
|
resets = <&reset 0>;
|
|
reset-names = "switch";
|
|
reg = <0x6 0x11010484 0x100>;
|
|
sgpio_in1: gpio@0 {
|
|
compatible = "microchip,sparx5-sgpio-bank";
|
|
reg = <0>;
|
|
gpio-controller;
|
|
#gpio-cells = <3>;
|
|
ngpios = <96>;
|
|
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
};
|
|
sgpio_out1: gpio@1 {
|
|
compatible = "microchip,sparx5-sgpio-bank";
|
|
reg = <1>;
|
|
gpio-controller;
|
|
#gpio-cells = <3>;
|
|
ngpios = <96>;
|
|
};
|
|
};
|
|
|
|
sgpio2: gpio@61101059c {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "microchip,sparx5-sgpio";
|
|
status = "disabled";
|
|
clocks = <&sys_clk>;
|
|
pinctrl-0 = <&sgpio2_pins>;
|
|
pinctrl-names = "default";
|
|
resets = <&reset 0>;
|
|
reset-names = "switch";
|
|
reg = <0x6 0x1101059c 0x100>;
|
|
sgpio_in2: gpio@0 {
|
|
reg = <0>;
|
|
compatible = "microchip,sparx5-sgpio-bank";
|
|
gpio-controller;
|
|
#gpio-cells = <3>;
|
|
ngpios = <96>;
|
|
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
};
|
|
sgpio_out2: gpio@1 {
|
|
compatible = "microchip,sparx5-sgpio-bank";
|
|
reg = <1>;
|
|
gpio-controller;
|
|
#gpio-cells = <3>;
|
|
ngpios = <96>;
|
|
};
|
|
};
|
|
|
|
i2c0: i2c@600101000 {
|
|
compatible = "snps,designware-i2c";
|
|
status = "disabled";
|
|
pinctrl-0 = <&i2c_pins>;
|
|
pinctrl-names = "default";
|
|
reg = <0x6 0x00101000 0x100>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
|
i2c-sda-hold-time-ns = <300>;
|
|
clock-frequency = <100000>;
|
|
clocks = <&ahb_clk>;
|
|
};
|
|
|
|
i2c1: i2c@600103000 {
|
|
compatible = "snps,designware-i2c";
|
|
status = "disabled";
|
|
pinctrl-0 = <&i2c2_pins>;
|
|
pinctrl-names = "default";
|
|
reg = <0x6 0x00103000 0x100>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
|
i2c-sda-hold-time-ns = <300>;
|
|
clock-frequency = <100000>;
|
|
clocks = <&ahb_clk>;
|
|
};
|
|
|
|
tmon0: tmon@610508110 {
|
|
compatible = "microchip,sparx5-temp";
|
|
reg = <0x6 0x10508110 0xc>;
|
|
#thermal-sensor-cells = <0>;
|
|
clocks = <&ahb_clk>;
|
|
};
|
|
|
|
mdio0: mdio@6110102b0 {
|
|
compatible = "mscc,ocelot-miim";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x6 0x110102b0 0x24>;
|
|
};
|
|
|
|
mdio1: mdio@6110102d4 {
|
|
compatible = "mscc,ocelot-miim";
|
|
status = "disabled";
|
|
pinctrl-0 = <&miim1_pins>;
|
|
pinctrl-names = "default";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x6 0x110102d4 0x24>;
|
|
};
|
|
|
|
mdio2: mdio@6110102f8 {
|
|
compatible = "mscc,ocelot-miim";
|
|
status = "disabled";
|
|
pinctrl-0 = <&miim2_pins>;
|
|
pinctrl-names = "default";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x6 0x110102d4 0x24>;
|
|
};
|
|
|
|
mdio3: mdio@61101031c {
|
|
compatible = "mscc,ocelot-miim";
|
|
status = "disabled";
|
|
pinctrl-0 = <&miim3_pins>;
|
|
pinctrl-names = "default";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x6 0x1101031c 0x24>;
|
|
};
|
|
|
|
serdes: serdes@10808000 {
|
|
compatible = "microchip,sparx5-serdes";
|
|
#phy-cells = <1>;
|
|
clocks = <&sys_clk>;
|
|
reg = <0x6 0x10808000 0x5d0000>;
|
|
};
|
|
|
|
switch: switch@0x600000000 {
|
|
compatible = "microchip,sparx5-switch";
|
|
reg = <0x6 0 0x401000>,
|
|
<0x6 0x10004000 0x7fc000>,
|
|
<0x6 0x11010000 0xaf0000>;
|
|
reg-names = "cpu", "dev", "gcb";
|
|
interrupt-names = "xtr", "fdma";
|
|
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
|
resets = <&reset 0>;
|
|
reset-names = "switch";
|
|
};
|
|
};
|
|
};
|