1
0
Fork 0
mirror of synced 2025-03-06 20:59:54 +01:00
linux/drivers/gpu/drm/amd/display/dc/dcn30
Aurabindo Pillai 158858bf1a drm/amd/display: rework macros for DWB register access
[Why]
A hack was used to access DWB register due to difference in the register
naming convention which was not compatible with existing SR/SRI* macros.
The additional macro needed were added to dwb ip specific header file
(dcnxx_dwb.h) instead of soc resource file (dcnxx_resource.c). Due to
this pattern, BASE macro had to be redefined in dcnxx_dwb.h, which in
turn needed us to undefine them in the resource file.

[How]
Add a separate macro for DWB access to the resource files that need it
instead of defining them in DWB ip header file. This will enable us to
reuse the BASE macro defined in the resource file.

Reviewed-by: Roman Li <Roman.Li@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-11-15 13:35:15 -05:00
..
dcn30_afmt.c drm/amd/display: Add VPG and AFMT low power support for DCN3.1 2021-09-14 15:57:11 -04:00
dcn30_afmt.h drm/amd/display: Add VPG and AFMT low power support for DCN3.1 2021-09-14 15:57:11 -04:00
dcn30_cm_common.c drm/amd/display: Correct algorithm for reversed gamma 2021-03-23 23:32:36 -04:00
dcn30_cm_common.h drm/amd/display: Add DCN3 DPP 2020-07-01 01:59:14 -04:00
dcn30_dccg.c drm/amd/display: Add interface for ADD & DROP PIXEL Registers 2021-06-08 12:22:42 -04:00
dcn30_dccg.h drm/amd/display: Add interface for ADD & DROP PIXEL Registers 2021-06-08 12:22:42 -04:00
dcn30_dio_link_encoder.c drm/amd/display: Add DP 2.0 BIOS and DMUB Support 2021-09-01 16:55:10 -04:00
dcn30_dio_link_encoder.h drm/amd/display: add dcn30_link_encoder_validate_output_with_stream to header 2020-12-15 11:34:04 -05:00
dcn30_dio_stream_encoder.c drm/amd/display: Program ACP related register 2022-07-05 16:13:18 -04:00
dcn30_dio_stream_encoder.h drm/amd/display: Program ACP related register 2022-07-05 16:13:18 -04:00
dcn30_dpp.c drm/amd/display: Use the same cursor info across features 2022-10-10 17:32:55 -04:00
dcn30_dpp.h drm/amd/display: Add dependant changes for DCN32/321 2022-06-03 16:43:38 -04:00
dcn30_dpp_cm.c drm/amd/display: Clean up some inconsistent indenting 2022-07-28 16:05:15 -04:00
dcn30_dwb.c drm/amd/display: Add DCN3 DWB 2020-07-01 01:59:14 -04:00
dcn30_dwb.h drm/amd/display: rework macros for DWB register access 2022-11-15 13:35:15 -05:00
dcn30_dwb_cm.c drm/amd/display: fix incorrect CM/TF programming sequence in dwb 2021-08-09 15:43:10 -04:00
dcn30_hubbub.c drm/amd/display: Add pstate verification and recovery for DCN31 2022-03-15 14:33:57 -04:00
dcn30_hubbub.h drm/amd/display: log additional register state for debug 2021-07-21 13:39:25 -04:00
dcn30_hubp.c drm/amd/display: For stereo keep "FLIP_ANY_FRAME" 2022-08-10 15:30:06 -04:00
dcn30_hubp.h drm/amd/display: Add missing mask for DCN3 2021-04-09 16:53:05 -04:00
dcn30_hwseq.c drm/amd/display: revert Disable DRR actions during state commit 2022-11-15 13:35:14 -05:00
dcn30_hwseq.h drm/amd/display: Firmware assisted MCLK switch and FS 2022-06-14 21:38:41 -04:00
dcn30_init.c drm/amd/display: rework recent update PHY state commit 2022-09-19 15:10:24 -04:00
dcn30_init.h drm/amd/display: Init function tables for DCN3 2020-07-01 01:59:15 -04:00
dcn30_mmhubbub.c drm/amd/display: fix function scopes 2021-12-13 16:34:26 -05:00
dcn30_mmhubbub.h drm/amd/display: rework macros for DWB register access 2022-11-15 13:35:15 -05:00
dcn30_mpc.c drm/amd/display: Clean up some inconsistent indenting 2022-07-28 16:05:15 -04:00
dcn30_mpc.h drm/amd/display: Prepare for new interfaces 2022-07-05 16:10:45 -04:00
dcn30_opp.h drm/amd/display: Add DCN3 OPP header 2020-07-01 01:59:14 -04:00
dcn30_optc.c drm/amd/display: Add events log to trace OPTC lock and unlock 2022-10-24 14:36:06 -04:00
dcn30_optc.h drm/amd/display: Fix a compilation failure on PowerPC caused by FPU code 2022-07-29 15:24:38 -04:00
dcn30_resource.c drm/amd/display: rework macros for DWB register access 2022-11-15 13:35:15 -05:00
dcn30_resource.h drm/amd/display: Add reinstate dram in the FPO logic 2022-07-25 17:17:36 -04:00
dcn30_vpg.c drm/amd/display: Fix issue with dynamic bpp change for DCN3x 2021-09-23 15:17:30 -04:00
dcn30_vpg.h drm/amd/display: Fix issue with dynamic bpp change for DCN3x 2021-09-23 15:17:30 -04:00
Makefile drm/amd/display: Remove FPU flags from DCN30 Makefile 2022-07-25 17:16:32 -04:00