Zhongwei 6f0bf2dbdd drm/amd/display: correct DML calc error of UrgentLatency ... [Why] The input UrgentLatency in CalculateUrgentBurstFactor of prefect check is wrong. [How] Correct to the correct one to keep same as HW formula Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Stylon Wang <stylon.wang@amd.com> Signed-off-by: Zhongwei <Zhongwei.Zhang@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2022-12-06 10:16:49 -05:00
..
dcn31_fpu.c	drm/amd/display: set per pipe dppclk to 0 when dpp is off	2022-11-29 11:03:38 -05:00
dcn31_fpu.h	drm/amd/display: fix unbounded requesting for high pixel rate modes on dcn315	2022-11-15 13:35:14 -05:00
display_mode_vba_31.c	drm/amd/display: correct DML calc error of UrgentLatency	2022-12-06 10:16:49 -05:00
display_mode_vba_31.h	drm/amd/display: Add DCN3.1 DML calculation support	2021-06-04 16:39:18 -04:00
display_rq_dlg_calc_31.c	drm/amd/display: Modify header inclusion pattern	2022-08-16 18:08:42 -04:00
display_rq_dlg_calc_31.h	drm/amd/display: Pass display_pipe_params_st as const in DML	2021-09-23 15:17:29 -04:00