Dillon Varone 2a2acdd7f8 drm/amd/display: Bypass DET swath fill check for max clocks ... [Description] If validating for max voltage level (therefore max clocks) always pass over the DET swath fill latency hiding check. Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com> Acked-by: Stylon Wang <stylon.wang@amd.com> Signed-off-by: Dillon Varone <Dillon.Varone@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2022-12-06 10:16:17 -05:00
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dcn32_fpu.c	drm/amd/display: Don't overwrite subvp pipe info in fast updates	2022-11-29 11:03:38 -05:00
dcn32_fpu.h	drm/amd/display: move remaining FPU code to dml folder	2022-10-27 15:12:08 -04:00
display_mode_vba_32.c	drm/amd/display: Bypass DET swath fill check for max clocks	2022-12-06 10:16:17 -05:00
display_mode_vba_32.h	drm/amd/display: Set max for prefetch lines on dcn32	2022-11-15 13:35:15 -05:00
display_mode_vba_util_32.c	drm/amd/display: Add check for DET fetch latency hiding for dcn32	2022-11-23 09:47:14 -05:00
display_mode_vba_util_32.h	drm/amd/display: Add check for DET fetch latency hiding for dcn32	2022-11-23 09:47:14 -05:00
display_rq_dlg_calc_32.c	drm/amd/display: Round up DST_after_scaler to nearest int	2022-11-01 11:48:06 -04:00
display_rq_dlg_calc_32.h	drm/amd/display: DML changes for DCN32/321	2022-06-03 16:43:37 -04:00