3c2d6ea279
IH ring1 is used to process GPU retry fault, overflow is enabled to drain retry fault because we want receive other interrupts while handling retry fault to recover range. There is no overflow flag set when wptr pass rptr. Use timestamp of rptr and wptr to handle overflow and drain retry fault. If fault timestamp goes backward, the fault is filtered and should not be processed. Drain fault is finished if processed_timestamp is equal to or larger than checkpoint timestamp. Add amdgpu_ih_functions interface decode_iv_ts for different chips to get timestamp from IV entry with different iv size and timestamp offset. amdgpu_ih_decode_iv_ts_helper is used for vega10, vega20, navi10. Signed-off-by: Philip Yang <Philip.Yang@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
110 lines
3.8 KiB
C
110 lines
3.8 KiB
C
/*
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* Copyright 2014 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __AMDGPU_IH_H__
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#define __AMDGPU_IH_H__
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/* Maximum number of IVs processed at once */
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#define AMDGPU_IH_MAX_NUM_IVS 32
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struct amdgpu_device;
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struct amdgpu_iv_entry;
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struct amdgpu_ih_regs {
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uint32_t ih_rb_base;
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uint32_t ih_rb_base_hi;
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uint32_t ih_rb_cntl;
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uint32_t ih_rb_wptr;
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uint32_t ih_rb_rptr;
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uint32_t ih_doorbell_rptr;
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uint32_t ih_rb_wptr_addr_lo;
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uint32_t ih_rb_wptr_addr_hi;
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uint32_t psp_reg_id;
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};
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/*
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* R6xx+ IH ring
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*/
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struct amdgpu_ih_ring {
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unsigned ring_size;
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uint32_t ptr_mask;
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u32 doorbell_index;
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bool use_doorbell;
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bool use_bus_addr;
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struct amdgpu_bo *ring_obj;
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volatile uint32_t *ring;
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uint64_t gpu_addr;
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uint64_t wptr_addr;
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volatile uint32_t *wptr_cpu;
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uint64_t rptr_addr;
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volatile uint32_t *rptr_cpu;
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bool enabled;
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unsigned rptr;
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struct amdgpu_ih_regs ih_regs;
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/* For waiting on IH processing at checkpoint. */
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wait_queue_head_t wait_process;
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uint64_t processed_timestamp;
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};
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/* return true if time stamp t2 is after t1 with 48bit wrap around */
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#define amdgpu_ih_ts_after(t1, t2) \
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(((int64_t)((t2) << 16) - (int64_t)((t1) << 16)) > 0LL)
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/* provided by the ih block */
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struct amdgpu_ih_funcs {
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/* ring read/write ptr handling, called from interrupt context */
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u32 (*get_wptr)(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih);
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void (*decode_iv)(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
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struct amdgpu_iv_entry *entry);
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uint64_t (*decode_iv_ts)(struct amdgpu_ih_ring *ih, u32 rptr,
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signed int offset);
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void (*set_rptr)(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih);
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};
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#define amdgpu_ih_get_wptr(adev, ih) (adev)->irq.ih_funcs->get_wptr((adev), (ih))
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#define amdgpu_ih_decode_iv(adev, iv) \
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(adev)->irq.ih_funcs->decode_iv((adev), (ih), (iv))
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#define amdgpu_ih_decode_iv_ts(adev, ih, rptr, offset) \
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(WARN_ON_ONCE(!(adev)->irq.ih_funcs->decode_iv_ts) ? 0 : \
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(adev)->irq.ih_funcs->decode_iv_ts((ih), (rptr), (offset)))
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#define amdgpu_ih_set_rptr(adev, ih) (adev)->irq.ih_funcs->set_rptr((adev), (ih))
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int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
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unsigned ring_size, bool use_bus_addr);
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void amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih);
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void amdgpu_ih_ring_write(struct amdgpu_ih_ring *ih, const uint32_t *iv,
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unsigned int num_dw);
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int amdgpu_ih_wait_on_checkpoint_process_ts(struct amdgpu_device *adev,
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struct amdgpu_ih_ring *ih);
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int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih);
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void amdgpu_ih_decode_iv_helper(struct amdgpu_device *adev,
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struct amdgpu_ih_ring *ih,
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struct amdgpu_iv_entry *entry);
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uint64_t amdgpu_ih_decode_iv_ts_helper(struct amdgpu_ih_ring *ih, u32 rptr,
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signed int offset);
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#endif
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