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linux/arch/x86/kernel/cpu
Zhang Rui edc0a2b595 x86/topology: Fix erroneous smp_num_siblings on Intel Hybrid platforms
Traditionally, all CPUs in a system have identical numbers of SMT
siblings.  That changes with hybrid processors where some logical CPUs
have a sibling and others have none.

Today, the CPU boot code sets the global variable smp_num_siblings when
every CPU thread is brought up. The last thread to boot will overwrite
it with the number of siblings of *that* thread. That last thread to
boot will "win". If the thread is a Pcore, smp_num_siblings == 2.  If it
is an Ecore, smp_num_siblings == 1.

smp_num_siblings describes if the *system* supports SMT.  It should
specify the maximum number of SMT threads among all cores.

Ensure that smp_num_siblings represents the system-wide maximum number
of siblings by always increasing its value. Never allow it to decrease.

On MeteorLake-P platform, this fixes a problem that the Ecore CPUs are
not updated in any cpu sibling map because the system is treated as an
UP system when probing Ecore CPUs.

Below shows part of the CPU topology information before and after the
fix, for both Pcore and Ecore CPU (cpu0 is Pcore, cpu 12 is Ecore).
...
-/sys/devices/system/cpu/cpu0/topology/package_cpus:000fff
-/sys/devices/system/cpu/cpu0/topology/package_cpus_list:0-11
+/sys/devices/system/cpu/cpu0/topology/package_cpus:3fffff
+/sys/devices/system/cpu/cpu0/topology/package_cpus_list:0-21
...
-/sys/devices/system/cpu/cpu12/topology/package_cpus:001000
-/sys/devices/system/cpu/cpu12/topology/package_cpus_list:12
+/sys/devices/system/cpu/cpu12/topology/package_cpus:3fffff
+/sys/devices/system/cpu/cpu12/topology/package_cpus_list:0-21

Notice that the "before" 'package_cpus_list' has only one CPU.  This
means that userspace tools like lscpu will see a little laptop like
an 11-socket system:

-Core(s) per socket:  1
-Socket(s):           11
+Core(s) per socket:  16
+Socket(s):           1

This is also expected to make the scheduler do rather wonky things
too.

[ dhansen: remove CPUID detail from changelog, add end user effects ]

CC: stable@kernel.org
Fixes: bbb65d2d36 ("x86: use cpuid vector 0xb when available for detecting cpu topology")
Fixes: 95f3d39ccf ("x86/cpu/topology: Provide detect_extended_topology_early()")
Suggested-by: Len Brown <len.brown@intel.com>
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lore.kernel.org/all/20230323015640.27906-1-rui.zhang%40intel.com
2023-05-25 10:48:42 -07:00
..
mce - Just cleanups and fixes this time around: make threshold_ktype const, 2023-04-25 09:56:33 -07:00
microcode Driver core changes for 6.4-rc1 2023-04-27 11:53:57 -07:00
mtrr x86/mtrr: Make message for disabled MTRRs more descriptive 2022-12-05 11:08:25 +01:00
resctrl Reduce redundant counter reads with resctrl refactoring 2023-04-28 09:30:51 -07:00
sgx fget() to fdget() conversions 2023-04-24 19:14:20 -07:00
.gitignore .gitignore: add SPDX License Identifier 2020-03-25 11:50:48 +01:00
acrn.c x86/acrn: Set up timekeeping 2022-08-04 11:11:59 +02:00
amd.c - Add Emerald Rapids to the list of Intel models supporting PPIN 2023-04-25 10:20:52 -07:00
aperfmperf.c x86/aperfmperf: Erase stale arch_freq_scale values when disabling frequency invariance readings 2023-01-16 10:19:15 +01:00
bugs.c x86/CPU/AMD: Make sure EFER[AIBRSE] is set 2023-03-16 11:50:00 +01:00
cacheinfo.c x86/cacheinfo: Remove unused trace variable 2023-02-11 10:43:31 +01:00
centaur.c x86/cpu/centaur: Add Centaur family >=7 CPUs initialization support 2020-09-11 10:53:19 +02:00
common.c x86/cpu: Add Xeon Emerald Rapids to list of CPUs that support PPIN 2023-04-05 20:01:52 +02:00
cpu.h x86/CPU/AMD: Make sure EFER[AIBRSE] is set 2023-03-16 11:50:00 +01:00
cpuid-deps.c x86/cpufeatures: Add Bandwidth Monitoring Event Configuration feature flag 2023-01-23 17:38:31 +01:00
cyrix.c x86/cyrix: include header linux/isa-dma.h 2022-07-26 14:03:12 -05:00
feat_ctl.c x86/cpu: Include the header of init_ia32_feat_ctl()'s prototype 2022-09-26 17:06:27 +02:00
hygon.c - Split MTRR and PAT init code to accomodate at least Xen PV and TDX 2022-12-13 14:56:56 -08:00
hypervisor.c x86/paravirt: Remove const mark from x86_hyper_xen_hvm variable 2019-07-17 08:09:59 +02:00
intel.c modules-6.4-rc1 2023-04-27 16:36:55 -07:00
intel_epb.c x86/intel_epb: Set Alder Lake N and Raptor Lake P normal EPB 2022-11-03 11:31:01 -07:00
intel_pconfig.c x86/pconfig: Detect PCONFIG targets 2018-03-12 12:10:54 +01:00
Makefile x86/cpu: Re-enable stackprotector 2022-10-17 16:40:56 +02:00
match.c x86/cpu: Add a steppings field to struct x86_cpu_id 2020-04-20 12:19:21 +02:00
mkcapflags.sh x86/cpu: Print VMX flags in /proc/cpuinfo using VMX_FEATURES_* 2020-01-13 18:36:02 +01:00
mshyperv.c - Add the necessary glue so that the kernel can run as a confidential 2023-04-25 10:48:08 -07:00
perfctr-watchdog.c x86/nmi_watchdog: Fix old-style NMI watchdog regression on old Intel CPUs 2021-06-10 10:04:40 +02:00
powerflags.c License cleanup: add SPDX GPL-2.0 license identifier to files with no license 2017-11-02 11:10:55 +01:00
proc.c x86/aperfmperf: Integrate the fallback code from show_cpuinfo() 2022-04-27 20:22:20 +02:00
rdrand.c x86/rdrand: Remove "nordrand" flag in favor of "random.trust_cpu" 2022-07-18 15:04:04 +02:00
scattered.c x86/cpufeatures: Add Bandwidth Monitoring Event Configuration feature flag 2023-01-23 17:38:31 +01:00
topology.c x86/topology: Fix erroneous smp_num_siblings on Intel Hybrid platforms 2023-05-25 10:48:42 -07:00
transmeta.c License cleanup: add SPDX GPL-2.0 license identifier to files with no license 2017-11-02 11:10:55 +01:00
tsx.c x86/cpu: Remove redundant extern x86_read_arch_cap_msr() 2023-01-10 12:40:24 +01:00
umc.c License cleanup: add SPDX GPL-2.0 license identifier to files with no license 2017-11-02 11:10:55 +01:00
umwait.c x86/umwait: move to use bus_get_dev_root() 2023-03-17 15:29:29 +01:00
vmware.c sched/clock/x86: Mark sched_clock() noinstr 2023-01-31 15:01:47 +01:00
vortex.c x86/CPU: Add support for Vortex CPUs 2021-10-21 15:49:07 +02:00
zhaoxin.c x86/cpu: Reinitialize IA32_FEAT_CTL MSR on BSP during wakeup 2020-06-15 14:18:37 +02:00