fea8826d5f
CP0_CMGCRBASE is not always available on CPS enabled system such as early proAptiv. For early SMP bring up where we can't safely access memeory, we patch the entry of CPS NMI vector to inject CMGCR address directly into register during early core bringup. For VPE bringup as the core is already coherenct at that point we just read the variable to obtain the address. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
52 lines
1.1 KiB
C
52 lines
1.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (C) 2013 Imagination Technologies
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* Author: Paul Burton <paul.burton@mips.com>
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*/
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#ifndef __MIPS_ASM_SMP_CPS_H__
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#define __MIPS_ASM_SMP_CPS_H__
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#define CPS_ENTRY_PATCH_INSNS 6
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#ifndef __ASSEMBLY__
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struct vpe_boot_config {
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unsigned long pc;
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unsigned long sp;
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unsigned long gp;
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};
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struct core_boot_config {
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atomic_t vpe_mask;
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struct vpe_boot_config *vpe_config;
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};
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extern struct core_boot_config *mips_cps_core_bootcfg;
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extern void mips_cps_core_entry(void);
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extern void mips_cps_core_init(void);
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extern void mips_cps_boot_vpes(struct core_boot_config *cfg, unsigned vpe);
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extern void mips_cps_pm_save(void);
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extern void mips_cps_pm_restore(void);
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extern void *mips_cps_core_entry_patch_end;
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#ifdef CONFIG_MIPS_CPS
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extern bool mips_cps_smp_in_use(void);
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#else /* !CONFIG_MIPS_CPS */
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static inline bool mips_cps_smp_in_use(void) { return false; }
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#endif /* !CONFIG_MIPS_CPS */
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#else /* __ASSEMBLY__ */
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.extern mips_cps_bootcfg;
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#endif /* __ASSEMBLY__ */
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#endif /* __MIPS_ASM_SMP_CPS_H__ */
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