b473d6a9d6
When the hardware reduces the power to the minimum possible, the power floor is notified via an interrupt. This can happen when user space requests a power limit via powercap RAPL interface, which forces the system to enter to the lowest power. This power floor indication can be used as a hint to resort to other methods of reducing power than via RAPL power limit. Before power floor status can be read or the firmware can trigger notifications regarding it, it needs to be configured via a mailbox command. The actual power floor status is read via bit 39 of MMIO offset 0x5B18 of the processor thermal PCI device. To show the current power floor status and get notification on a sysfs attribute, add 2 new attributes to /sys/bus/pci/devices/0000\:00\:04.0/power_limits/ power_floor_enable : This attribute is present when power floor notifications are supported. This attribute allows to enable/disable power floor notifications. power_floor_status : This attribute is present when power floor notifications are supported. When enabled via power_floor_enable, this attribute shows the current power floor status. The power floor implementation provides interfaces which are called from the sysfs callbacks to enable/disable and read power floor status. It also provides two additional interfaces to check if the current processor thermal device interrupt is for power floor status and to send notifications to user space. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> [ rjw: Changelog and documentation changes edits ] Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
123 lines
4.2 KiB
C
123 lines
4.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* processor_thermal_device.h
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* Copyright (c) 2020, Intel Corporation.
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*/
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#ifndef __PROCESSOR_THERMAL_DEVICE_H__
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#define __PROCESSOR_THERMAL_DEVICE_H__
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#include <linux/intel_rapl.h>
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#define PCI_DEVICE_ID_INTEL_ADL_THERMAL 0x461d
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#define PCI_DEVICE_ID_INTEL_ARL_S_THERMAL 0xAD03
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#define PCI_DEVICE_ID_INTEL_BDW_THERMAL 0x1603
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#define PCI_DEVICE_ID_INTEL_BSW_THERMAL 0x22DC
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#define PCI_DEVICE_ID_INTEL_BXT0_THERMAL 0x0A8C
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#define PCI_DEVICE_ID_INTEL_BXT1_THERMAL 0x1A8C
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#define PCI_DEVICE_ID_INTEL_BXTX_THERMAL 0x4A8C
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#define PCI_DEVICE_ID_INTEL_BXTP_THERMAL 0x5A8C
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#define PCI_DEVICE_ID_INTEL_CNL_THERMAL 0x5a03
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#define PCI_DEVICE_ID_INTEL_CFL_THERMAL 0x3E83
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#define PCI_DEVICE_ID_INTEL_GLK_THERMAL 0x318C
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#define PCI_DEVICE_ID_INTEL_HSB_THERMAL 0x0A03
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#define PCI_DEVICE_ID_INTEL_ICL_THERMAL 0x8a03
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#define PCI_DEVICE_ID_INTEL_JSL_THERMAL 0x4E03
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#define PCI_DEVICE_ID_INTEL_MTLP_THERMAL 0x7D03
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#define PCI_DEVICE_ID_INTEL_RPL_THERMAL 0xA71D
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#define PCI_DEVICE_ID_INTEL_SKL_THERMAL 0x1903
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#define PCI_DEVICE_ID_INTEL_TGL_THERMAL 0x9A03
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struct power_config {
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u32 index;
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u32 min_uw;
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u32 max_uw;
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u32 tmin_us;
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u32 tmax_us;
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u32 step_uw;
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};
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struct proc_thermal_device {
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struct device *dev;
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struct acpi_device *adev;
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struct power_config power_limits[2];
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struct int34x_thermal_zone *int340x_zone;
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struct intel_soc_dts_sensors *soc_dts;
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u32 mmio_feature_mask;
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void __iomem *mmio_base;
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void *priv_data;
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};
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struct rapl_mmio_regs {
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u64 reg_unit;
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u64 regs[RAPL_DOMAIN_MAX][RAPL_DOMAIN_REG_MAX];
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int limits[RAPL_DOMAIN_MAX];
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};
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#define PROC_THERMAL_FEATURE_NONE 0x00
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#define PROC_THERMAL_FEATURE_RAPL 0x01
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#define PROC_THERMAL_FEATURE_FIVR 0x02
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#define PROC_THERMAL_FEATURE_DVFS 0x04
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#define PROC_THERMAL_FEATURE_WT_REQ 0x08
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#define PROC_THERMAL_FEATURE_DLVR 0x10
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#define PROC_THERMAL_FEATURE_WT_HINT 0x20
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#define PROC_THERMAL_FEATURE_POWER_FLOOR 0x40
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#if IS_ENABLED(CONFIG_PROC_THERMAL_MMIO_RAPL)
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int proc_thermal_rapl_add(struct pci_dev *pdev, struct proc_thermal_device *proc_priv);
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void proc_thermal_rapl_remove(void);
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#else
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static int __maybe_unused proc_thermal_rapl_add(struct pci_dev *pdev,
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struct proc_thermal_device *proc_priv)
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{
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return 0;
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}
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static void __maybe_unused proc_thermal_rapl_remove(void)
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{
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}
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#endif
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int proc_thermal_rfim_add(struct pci_dev *pdev, struct proc_thermal_device *proc_priv);
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void proc_thermal_rfim_remove(struct pci_dev *pdev);
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int proc_thermal_wt_req_add(struct pci_dev *pdev, struct proc_thermal_device *proc_priv);
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void proc_thermal_wt_req_remove(struct pci_dev *pdev);
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#define MBOX_CMD_WORKLOAD_TYPE_READ 0x0E
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#define MBOX_CMD_WORKLOAD_TYPE_WRITE 0x0F
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#define MBOX_DATA_BIT_AC_DC 30
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#define MBOX_DATA_BIT_VALID 31
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#define SOC_WT_RES_INT_STATUS_OFFSET 0x5B18
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#define SOC_WT_RES_INT_STATUS_MASK GENMASK_ULL(3, 2)
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int proc_thermal_read_power_floor_status(struct proc_thermal_device *proc_priv);
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int proc_thermal_power_floor_set_state(struct proc_thermal_device *proc_priv, bool enable);
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bool proc_thermal_power_floor_get_state(struct proc_thermal_device *proc_priv);
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void proc_thermal_power_floor_intr_callback(struct pci_dev *pdev,
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struct proc_thermal_device *proc_priv);
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bool proc_thermal_check_power_floor_intr(struct proc_thermal_device *proc_priv);
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int processor_thermal_send_mbox_read_cmd(struct pci_dev *pdev, u16 id, u64 *resp);
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int processor_thermal_send_mbox_write_cmd(struct pci_dev *pdev, u16 id, u32 data);
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int processor_thermal_mbox_interrupt_config(struct pci_dev *pdev, bool enable, int enable_bit,
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int time_window);
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int proc_thermal_add(struct device *dev, struct proc_thermal_device *priv);
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void proc_thermal_remove(struct proc_thermal_device *proc_priv);
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int proc_thermal_wt_hint_add(struct pci_dev *pdev, struct proc_thermal_device *proc_priv);
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void proc_thermal_wt_hint_remove(struct pci_dev *pdev);
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void proc_thermal_wt_intr_callback(struct pci_dev *pdev, struct proc_thermal_device *proc_priv);
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bool proc_thermal_check_wt_intr(struct proc_thermal_device *proc_priv);
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int proc_thermal_suspend(struct device *dev);
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int proc_thermal_resume(struct device *dev);
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int proc_thermal_mmio_add(struct pci_dev *pdev,
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struct proc_thermal_device *proc_priv,
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kernel_ulong_t feature_mask);
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void proc_thermal_mmio_remove(struct pci_dev *pdev, struct proc_thermal_device *proc_priv);
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#endif
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