dd28a3cb92
Some features like workload type prediction and power floor events require interrupt support to avoid polling. Here interrupts are enabled and disabled via sending mailbox commands. The mailbox command ID is 0x1E for read and 0x1F for write. The interrupt configuration will require mutex protection as it involves read-modify-write operation. Since mutex are already used in the mailbox read/write functions: send_mbox_write_cmd() and send_mbox_read_cmd(), there will be double locking. But, this can be avoided by moving mutexes from mailbox read/write processing functions to the callers: processor_thermal_send_mbox_[read|write]_cmd(). Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> [ rjw: Adjust subject, fix up computation ] Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
158 lines
3.6 KiB
C
158 lines
3.6 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* processor thermal device mailbox driver for Workload type hints
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* Copyright (c) 2020, Intel Corporation.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/io-64-nonatomic-lo-hi.h>
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#include "processor_thermal_device.h"
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#define MBOX_OFFSET_DATA 0x5810
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#define MBOX_OFFSET_INTERFACE 0x5818
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#define MBOX_BUSY_BIT 31
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#define MBOX_RETRY_COUNT 100
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static DEFINE_MUTEX(mbox_lock);
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static int wait_for_mbox_ready(struct proc_thermal_device *proc_priv)
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{
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u32 retries, data;
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int ret;
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/* Poll for rb bit == 0 */
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retries = MBOX_RETRY_COUNT;
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do {
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data = readl(proc_priv->mmio_base + MBOX_OFFSET_INTERFACE);
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if (data & BIT_ULL(MBOX_BUSY_BIT)) {
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ret = -EBUSY;
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continue;
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}
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ret = 0;
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break;
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} while (--retries);
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return ret;
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}
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static int send_mbox_write_cmd(struct pci_dev *pdev, u16 id, u32 data)
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{
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struct proc_thermal_device *proc_priv;
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u32 reg_data;
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int ret;
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proc_priv = pci_get_drvdata(pdev);
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ret = wait_for_mbox_ready(proc_priv);
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if (ret)
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return ret;
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writel(data, (proc_priv->mmio_base + MBOX_OFFSET_DATA));
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/* Write command register */
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reg_data = BIT_ULL(MBOX_BUSY_BIT) | id;
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writel(reg_data, (proc_priv->mmio_base + MBOX_OFFSET_INTERFACE));
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return wait_for_mbox_ready(proc_priv);
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}
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static int send_mbox_read_cmd(struct pci_dev *pdev, u16 id, u64 *resp)
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{
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struct proc_thermal_device *proc_priv;
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u32 reg_data;
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int ret;
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proc_priv = pci_get_drvdata(pdev);
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ret = wait_for_mbox_ready(proc_priv);
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if (ret)
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return ret;
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/* Write command register */
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reg_data = BIT_ULL(MBOX_BUSY_BIT) | id;
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writel(reg_data, (proc_priv->mmio_base + MBOX_OFFSET_INTERFACE));
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ret = wait_for_mbox_ready(proc_priv);
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if (ret)
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return ret;
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if (id == MBOX_CMD_WORKLOAD_TYPE_READ)
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*resp = readl(proc_priv->mmio_base + MBOX_OFFSET_DATA);
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else
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*resp = readq(proc_priv->mmio_base + MBOX_OFFSET_DATA);
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return 0;
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}
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int processor_thermal_send_mbox_read_cmd(struct pci_dev *pdev, u16 id, u64 *resp)
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{
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int ret;
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mutex_lock(&mbox_lock);
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ret = send_mbox_read_cmd(pdev, id, resp);
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mutex_unlock(&mbox_lock);
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return ret;
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}
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EXPORT_SYMBOL_NS_GPL(processor_thermal_send_mbox_read_cmd, INT340X_THERMAL);
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int processor_thermal_send_mbox_write_cmd(struct pci_dev *pdev, u16 id, u32 data)
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{
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int ret;
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mutex_lock(&mbox_lock);
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ret = send_mbox_write_cmd(pdev, id, data);
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mutex_unlock(&mbox_lock);
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return ret;
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}
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EXPORT_SYMBOL_NS_GPL(processor_thermal_send_mbox_write_cmd, INT340X_THERMAL);
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#define MBOX_CAMARILLO_RD_INTR_CONFIG 0x1E
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#define MBOX_CAMARILLO_WR_INTR_CONFIG 0x1F
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#define WLT_TW_MASK GENMASK_ULL(30, 24)
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#define SOC_PREDICTION_TW_SHIFT 24
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int processor_thermal_mbox_interrupt_config(struct pci_dev *pdev, bool enable,
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int enable_bit, int time_window)
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{
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u64 data;
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int ret;
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if (!pdev)
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return -ENODEV;
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mutex_lock(&mbox_lock);
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/* Do read modify write for MBOX_CAMARILLO_RD_INTR_CONFIG */
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ret = send_mbox_read_cmd(pdev, MBOX_CAMARILLO_RD_INTR_CONFIG, &data);
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if (ret) {
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dev_err(&pdev->dev, "MBOX_CAMARILLO_RD_INTR_CONFIG failed\n");
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goto unlock;
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}
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if (time_window >= 0) {
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data &= ~WLT_TW_MASK;
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/* Program notification delay */
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data |= ((u64)time_window << SOC_PREDICTION_TW_SHIFT) & WLT_TW_MASK;
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}
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if (enable)
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data |= BIT(enable_bit);
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else
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data &= ~BIT(enable_bit);
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ret = send_mbox_write_cmd(pdev, MBOX_CAMARILLO_WR_INTR_CONFIG, data);
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if (ret)
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dev_err(&pdev->dev, "MBOX_CAMARILLO_WR_INTR_CONFIG failed\n");
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unlock:
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mutex_unlock(&mbox_lock);
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return ret;
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}
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EXPORT_SYMBOL_NS_GPL(processor_thermal_mbox_interrupt_config, INT340X_THERMAL);
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MODULE_LICENSE("GPL v2");
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