6ca445d8af
Commitc97bf62996("riscv: Fix text patching when IPI are used") converted ftrace_make_nop() to use patch_insn_write() which does not emit any icache flush relying entirely on __ftrace_modify_code() to do that. But we missed that ftrace_make_nop() was called very early directly when converting mcount calls into nops (actually on riscv it converts 2B nops emitted by the compiler into 4B nops). This caused crashes on multiple HW as reported by Conor and Björn since the booting core could have half-patched instructions in its icache which would trigger an illegal instruction trap: fix this by emitting a local flush icache when early patching nops. Fixes:c97bf62996("riscv: Fix text patching when IPI are used") Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> Reported-by: Conor Dooley <conor.dooley@microchip.com> Tested-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Björn Töpel <bjorn@rivosinc.com> Tested-by: Björn Töpel <bjorn@rivosinc.com> Link: https://lore.kernel.org/r/20240523115134.70380-1-alexghiti@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
85 lines
2.2 KiB
C
85 lines
2.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2015 Regents of the University of California
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*/
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#ifndef _ASM_RISCV_CACHEFLUSH_H
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#define _ASM_RISCV_CACHEFLUSH_H
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#include <linux/mm.h>
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static inline void local_flush_icache_all(void)
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{
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asm volatile ("fence.i" ::: "memory");
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}
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static inline void local_flush_icache_range(unsigned long start,
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unsigned long end)
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{
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local_flush_icache_all();
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}
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#define PG_dcache_clean PG_arch_1
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static inline void flush_dcache_folio(struct folio *folio)
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{
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if (test_bit(PG_dcache_clean, &folio->flags))
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clear_bit(PG_dcache_clean, &folio->flags);
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}
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#define flush_dcache_folio flush_dcache_folio
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#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
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static inline void flush_dcache_page(struct page *page)
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{
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flush_dcache_folio(page_folio(page));
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}
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/*
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* RISC-V doesn't have an instruction to flush parts of the instruction cache,
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* so instead we just flush the whole thing.
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*/
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#define flush_icache_range(start, end) flush_icache_all()
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#define flush_icache_user_page(vma, pg, addr, len) \
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do { \
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if (vma->vm_flags & VM_EXEC) \
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flush_icache_mm(vma->vm_mm, 0); \
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} while (0)
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#ifdef CONFIG_64BIT
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#define flush_cache_vmap(start, end) flush_tlb_kernel_range(start, end)
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#define flush_cache_vmap_early(start, end) local_flush_tlb_kernel_range(start, end)
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#endif
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#ifndef CONFIG_SMP
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#define flush_icache_all() local_flush_icache_all()
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#define flush_icache_mm(mm, local) flush_icache_all()
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#else /* CONFIG_SMP */
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void flush_icache_all(void);
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void flush_icache_mm(struct mm_struct *mm, bool local);
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#endif /* CONFIG_SMP */
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extern unsigned int riscv_cbom_block_size;
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extern unsigned int riscv_cboz_block_size;
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void riscv_init_cbo_blocksizes(void);
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#ifdef CONFIG_RISCV_DMA_NONCOHERENT
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void riscv_noncoherent_supported(void);
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void __init riscv_set_dma_cache_alignment(void);
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#else
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static inline void riscv_noncoherent_supported(void) {}
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static inline void riscv_set_dma_cache_alignment(void) {}
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#endif
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/*
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* Bits in sys_riscv_flush_icache()'s flags argument.
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*/
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#define SYS_RISCV_FLUSH_ICACHE_LOCAL 1UL
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#define SYS_RISCV_FLUSH_ICACHE_ALL (SYS_RISCV_FLUSH_ICACHE_LOCAL)
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#include <asm-generic/cacheflush.h>
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#endif /* _ASM_RISCV_CACHEFLUSH_H */
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