c150b809f7
* Support for various vector-accelerated crypto routines.
* Hibernation is now enabled for portable kernel builds.
* mmap_rnd_bits_max is larger on systems with larger VAs.
* Support for fast GUP.
* Support for membarrier-based instruction cache synchronization.
* Support for the Andes hart-level interrupt controller and PMU.
* Some cleanups around unaligned access speed probing and Kconfig
settings.
* Support for ACPI LPI and CPPC.
* Various cleanus related to barriers.
* A handful of fixes.
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Merge tag 'riscv-for-linus-6.9-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
Pull RISC-V updates from Palmer Dabbelt:
- Support for various vector-accelerated crypto routines
- Hibernation is now enabled for portable kernel builds
- mmap_rnd_bits_max is larger on systems with larger VAs
- Support for fast GUP
- Support for membarrier-based instruction cache synchronization
- Support for the Andes hart-level interrupt controller and PMU
- Some cleanups around unaligned access speed probing and Kconfig
settings
- Support for ACPI LPI and CPPC
- Various cleanus related to barriers
- A handful of fixes
* tag 'riscv-for-linus-6.9-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (66 commits)
riscv: Fix syscall wrapper for >word-size arguments
crypto: riscv - add vector crypto accelerated AES-CBC-CTS
crypto: riscv - parallelize AES-CBC decryption
riscv: Only flush the mm icache when setting an exec pte
riscv: Use kcalloc() instead of kzalloc()
riscv/barrier: Add missing space after ','
riscv/barrier: Consolidate fence definitions
riscv/barrier: Define RISCV_FULL_BARRIER
riscv/barrier: Define __{mb,rmb,wmb}
RISC-V: defconfig: Enable CONFIG_ACPI_CPPC_CPUFREQ
cpufreq: Move CPPC configs to common Kconfig and add RISC-V
ACPI: RISC-V: Add CPPC driver
ACPI: Enable ACPI_PROCESSOR for RISC-V
ACPI: RISC-V: Add LPI driver
cpuidle: RISC-V: Move few functions to arch/riscv
riscv: Introduce set_compat_task() in asm/compat.h
riscv: Introduce is_compat_thread() into compat.h
riscv: add compile-time test into is_compat_task()
riscv: Replace direct thread flag check with is_compat_task()
riscv: Improve arch_get_mmap_end() macro
...
96 lines
2.9 KiB
C
96 lines
2.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copied from arch/arm64/include/asm/hwcap.h
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*
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* Copyright (C) 2012 ARM Ltd.
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* Copyright (C) 2017 SiFive
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*/
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#ifndef _ASM_RISCV_HWCAP_H
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#define _ASM_RISCV_HWCAP_H
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#include <uapi/asm/hwcap.h>
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#define RISCV_ISA_EXT_a ('a' - 'a')
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#define RISCV_ISA_EXT_c ('c' - 'a')
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#define RISCV_ISA_EXT_d ('d' - 'a')
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#define RISCV_ISA_EXT_f ('f' - 'a')
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#define RISCV_ISA_EXT_h ('h' - 'a')
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#define RISCV_ISA_EXT_i ('i' - 'a')
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#define RISCV_ISA_EXT_m ('m' - 'a')
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#define RISCV_ISA_EXT_q ('q' - 'a')
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#define RISCV_ISA_EXT_v ('v' - 'a')
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/*
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* These macros represent the logical IDs of each multi-letter RISC-V ISA
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* extension and are used in the ISA bitmap. The logical IDs start from
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* RISCV_ISA_EXT_BASE, which allows the 0-25 range to be reserved for single
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* letter extensions. The maximum, RISCV_ISA_EXT_MAX, is defined in order
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* to allocate the bitmap and may be increased when necessary.
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*
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* New extensions should just be added to the bottom, rather than added
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* alphabetically, in order to avoid unnecessary shuffling.
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*/
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#define RISCV_ISA_EXT_BASE 26
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#define RISCV_ISA_EXT_SSCOFPMF 26
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#define RISCV_ISA_EXT_SSTC 27
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#define RISCV_ISA_EXT_SVINVAL 28
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#define RISCV_ISA_EXT_SVPBMT 29
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#define RISCV_ISA_EXT_ZBB 30
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#define RISCV_ISA_EXT_ZICBOM 31
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#define RISCV_ISA_EXT_ZIHINTPAUSE 32
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#define RISCV_ISA_EXT_SVNAPOT 33
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#define RISCV_ISA_EXT_ZICBOZ 34
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#define RISCV_ISA_EXT_SMAIA 35
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#define RISCV_ISA_EXT_SSAIA 36
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#define RISCV_ISA_EXT_ZBA 37
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#define RISCV_ISA_EXT_ZBS 38
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#define RISCV_ISA_EXT_ZICNTR 39
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#define RISCV_ISA_EXT_ZICSR 40
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#define RISCV_ISA_EXT_ZIFENCEI 41
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#define RISCV_ISA_EXT_ZIHPM 42
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#define RISCV_ISA_EXT_SMSTATEEN 43
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#define RISCV_ISA_EXT_ZICOND 44
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#define RISCV_ISA_EXT_ZBC 45
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#define RISCV_ISA_EXT_ZBKB 46
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#define RISCV_ISA_EXT_ZBKC 47
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#define RISCV_ISA_EXT_ZBKX 48
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#define RISCV_ISA_EXT_ZKND 49
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#define RISCV_ISA_EXT_ZKNE 50
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#define RISCV_ISA_EXT_ZKNH 51
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#define RISCV_ISA_EXT_ZKR 52
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#define RISCV_ISA_EXT_ZKSED 53
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#define RISCV_ISA_EXT_ZKSH 54
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#define RISCV_ISA_EXT_ZKT 55
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#define RISCV_ISA_EXT_ZVBB 56
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#define RISCV_ISA_EXT_ZVBC 57
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#define RISCV_ISA_EXT_ZVKB 58
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#define RISCV_ISA_EXT_ZVKG 59
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#define RISCV_ISA_EXT_ZVKNED 60
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#define RISCV_ISA_EXT_ZVKNHA 61
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#define RISCV_ISA_EXT_ZVKNHB 62
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#define RISCV_ISA_EXT_ZVKSED 63
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#define RISCV_ISA_EXT_ZVKSH 64
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#define RISCV_ISA_EXT_ZVKT 65
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#define RISCV_ISA_EXT_ZFH 66
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#define RISCV_ISA_EXT_ZFHMIN 67
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#define RISCV_ISA_EXT_ZIHINTNTL 68
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#define RISCV_ISA_EXT_ZVFH 69
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#define RISCV_ISA_EXT_ZVFHMIN 70
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#define RISCV_ISA_EXT_ZFA 71
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#define RISCV_ISA_EXT_ZTSO 72
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#define RISCV_ISA_EXT_ZACAS 73
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#define RISCV_ISA_EXT_XANDESPMU 74
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#define RISCV_ISA_EXT_XLINUXENVCFG 127
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#define RISCV_ISA_EXT_MAX 128
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#define RISCV_ISA_EXT_INVALID U32_MAX
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#ifdef CONFIG_RISCV_M_MODE
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#define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SMAIA
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#else
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#define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SSAIA
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#endif
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#endif /* _ASM_RISCV_HWCAP_H */
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