79997eda0d
The timebase-frequency on PolarFire SoC is not set by an oscillator on the board, but rather by an internal divider, so move the property to mpfs.dtsi. This looks to be copy-pasta from the SiFive Unleashed as the comments in both places were almost identical. In the Unleashed's case this looks to actually be valid, as the clock is provided by a crystal on the PCB. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> --- CC: Conor Dooley <conor.dooley@microchip.com> CC: Daire McNamara <daire.mcnamara@microchip.com> CC: Rob Herring <robh+dt@kernel.org> CC: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> CC: Paul Walmsley <paul.walmsley@sifive.com> CC: Palmer Dabbelt <palmer@dabbelt.com> CC: linux-riscv@lists.infradead.org CC: devicetree@vger.kernel.org
89 lines
1.3 KiB
Text
89 lines
1.3 KiB
Text
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/* Copyright (c) 2020-2022 Microchip Technology Inc */
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/dts-v1/;
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#include "mpfs.dtsi"
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#include "mpfs-polarberry-fabric.dtsi"
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/ {
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model = "Sundance PolarBerry";
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compatible = "sundance,polarberry", "microchip,mpfs";
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aliases {
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ethernet0 = &mac1;
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serial0 = &mmuart0;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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ddrc_cache_lo: memory@80000000 {
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device_type = "memory";
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reg = <0x0 0x80000000 0x0 0x2e000000>;
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};
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ddrc_cache_hi: memory@1000000000 {
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device_type = "memory";
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reg = <0x10 0x00000000 0x0 0xC0000000>;
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};
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};
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/*
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* phy0 is connected to mac0, but the port itself is on the (optional) carrier
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* board.
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*/
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&mac0 {
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phy-mode = "sgmii";
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phy-handle = <&phy0>;
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status = "disabled";
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};
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&mac1 {
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phy-mode = "sgmii";
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phy-handle = <&phy1>;
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status = "okay";
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phy1: ethernet-phy@5 {
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reg = <5>;
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};
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phy0: ethernet-phy@4 {
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reg = <4>;
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};
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};
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&mbox {
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status = "okay";
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};
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&mmc {
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bus-width = <4>;
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disable-wp;
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cap-sd-highspeed;
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cap-mmc-highspeed;
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mmc-ddr-1_8v;
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mmc-hs200-1_8v;
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sd-uhs-sdr12;
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sd-uhs-sdr25;
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sd-uhs-sdr50;
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sd-uhs-sdr104;
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status = "okay";
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};
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&mmuart0 {
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status = "okay";
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};
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&refclk {
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clock-frequency = <125000000>;
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};
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&rtc {
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status = "okay";
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};
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&syscontroller {
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status = "okay";
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};
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