483fd65ce2
The function adf_send_admin_tl_start() enables the telemetry (TL)
feature on a QAT device by sending the ICP_QAT_FW_TL_START message to
the firmware. This triggers the FW to start writing TL data to a DMA
buffer in memory and returns an array containing the number of
accelerators of each type (slices) supported by this HW.
The pointer to this array is stored in the adf_tl_hw_data data
structure called slice_cnt.
The array slice_cnt is then used in the function tl_print_dev_data()
to report in debugfs only statistics about the supported accelerators.
An incorrect value of the elements in slice_cnt might lead to an out
of bounds memory read.
At the moment, there isn't an implementation of FW that returns a wrong
value, but for robustness validate the slice count array returned by FW.
Fixes: 69e7649f7c ("crypto: qat - add support for device telemetry")
Signed-off-by: Lucas Segarra Fernandez <lucas.segarra.fernandez@intel.com>
Reviewed-by: Damian Muszynski <damian.muszynski@intel.com>
Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
154 lines
6.1 KiB
C
154 lines
6.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright (c) 2023 Intel Corporation. */
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#include <linux/export.h>
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#include <linux/kernel.h>
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#include "adf_gen4_tl.h"
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#include "adf_telemetry.h"
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#include "adf_tl_debugfs.h"
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#define ADF_GEN4_TL_DEV_REG_OFF(reg) ADF_TL_DEV_REG_OFF(reg, gen4)
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#define ADF_GEN4_TL_RP_REG_OFF(reg) ADF_TL_RP_REG_OFF(reg, gen4)
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#define ADF_GEN4_TL_SL_UTIL_COUNTER(_name) \
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ADF_TL_COUNTER("util_" #_name, \
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ADF_TL_SIMPLE_COUNT, \
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ADF_TL_SLICE_REG_OFF(_name, reg_tm_slice_util, gen4))
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#define ADF_GEN4_TL_SL_EXEC_COUNTER(_name) \
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ADF_TL_COUNTER("exec_" #_name, \
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ADF_TL_SIMPLE_COUNT, \
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ADF_TL_SLICE_REG_OFF(_name, reg_tm_slice_exec_cnt, gen4))
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/* Device level counters. */
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static const struct adf_tl_dbg_counter dev_counters[] = {
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/* PCIe partial transactions. */
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ADF_TL_COUNTER(PCI_TRANS_CNT_NAME, ADF_TL_SIMPLE_COUNT,
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ADF_GEN4_TL_DEV_REG_OFF(reg_tl_pci_trans_cnt)),
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/* Max read latency[ns]. */
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ADF_TL_COUNTER(MAX_RD_LAT_NAME, ADF_TL_COUNTER_NS,
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ADF_GEN4_TL_DEV_REG_OFF(reg_tl_rd_lat_max)),
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/* Read latency average[ns]. */
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ADF_TL_COUNTER_LATENCY(RD_LAT_ACC_NAME, ADF_TL_COUNTER_NS_AVG,
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ADF_GEN4_TL_DEV_REG_OFF(reg_tl_rd_lat_acc),
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ADF_GEN4_TL_DEV_REG_OFF(reg_tl_rd_cmpl_cnt)),
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/* Max get to put latency[ns]. */
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ADF_TL_COUNTER(MAX_LAT_NAME, ADF_TL_COUNTER_NS,
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ADF_GEN4_TL_DEV_REG_OFF(reg_tl_gp_lat_max)),
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/* Get to put latency average[ns]. */
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ADF_TL_COUNTER_LATENCY(LAT_ACC_NAME, ADF_TL_COUNTER_NS_AVG,
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ADF_GEN4_TL_DEV_REG_OFF(reg_tl_gp_lat_acc),
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ADF_GEN4_TL_DEV_REG_OFF(reg_tl_ae_put_cnt)),
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/* PCIe write bandwidth[Mbps]. */
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ADF_TL_COUNTER(BW_IN_NAME, ADF_TL_COUNTER_MBPS,
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ADF_GEN4_TL_DEV_REG_OFF(reg_tl_bw_in)),
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/* PCIe read bandwidth[Mbps]. */
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ADF_TL_COUNTER(BW_OUT_NAME, ADF_TL_COUNTER_MBPS,
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ADF_GEN4_TL_DEV_REG_OFF(reg_tl_bw_out)),
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/* Page request latency average[ns]. */
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ADF_TL_COUNTER_LATENCY(PAGE_REQ_LAT_NAME, ADF_TL_COUNTER_NS_AVG,
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ADF_GEN4_TL_DEV_REG_OFF(reg_tl_at_page_req_lat_acc),
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ADF_GEN4_TL_DEV_REG_OFF(reg_tl_at_page_req_cnt)),
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/* Page translation latency average[ns]. */
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ADF_TL_COUNTER_LATENCY(AT_TRANS_LAT_NAME, ADF_TL_COUNTER_NS_AVG,
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ADF_GEN4_TL_DEV_REG_OFF(reg_tl_at_trans_lat_acc),
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ADF_GEN4_TL_DEV_REG_OFF(reg_tl_at_trans_lat_cnt)),
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/* Maximum uTLB used. */
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ADF_TL_COUNTER(AT_MAX_UTLB_USED_NAME, ADF_TL_SIMPLE_COUNT,
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ADF_GEN4_TL_DEV_REG_OFF(reg_tl_at_max_tlb_used)),
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};
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/* Slice utilization counters. */
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static const struct adf_tl_dbg_counter sl_util_counters[ADF_TL_SL_CNT_COUNT] = {
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/* Compression slice utilization. */
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ADF_GEN4_TL_SL_UTIL_COUNTER(cpr),
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/* Translator slice utilization. */
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ADF_GEN4_TL_SL_UTIL_COUNTER(xlt),
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/* Decompression slice utilization. */
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ADF_GEN4_TL_SL_UTIL_COUNTER(dcpr),
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/* PKE utilization. */
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ADF_GEN4_TL_SL_UTIL_COUNTER(pke),
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/* Wireless Authentication slice utilization. */
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ADF_GEN4_TL_SL_UTIL_COUNTER(wat),
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/* Wireless Cipher slice utilization. */
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ADF_GEN4_TL_SL_UTIL_COUNTER(wcp),
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/* UCS slice utilization. */
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ADF_GEN4_TL_SL_UTIL_COUNTER(ucs),
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/* Cipher slice utilization. */
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ADF_GEN4_TL_SL_UTIL_COUNTER(cph),
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/* Authentication slice utilization. */
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ADF_GEN4_TL_SL_UTIL_COUNTER(ath),
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};
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/* Slice execution counters. */
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static const struct adf_tl_dbg_counter sl_exec_counters[ADF_TL_SL_CNT_COUNT] = {
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/* Compression slice execution count. */
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ADF_GEN4_TL_SL_EXEC_COUNTER(cpr),
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/* Translator slice execution count. */
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ADF_GEN4_TL_SL_EXEC_COUNTER(xlt),
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/* Decompression slice execution count. */
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ADF_GEN4_TL_SL_EXEC_COUNTER(dcpr),
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/* PKE execution count. */
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ADF_GEN4_TL_SL_EXEC_COUNTER(pke),
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/* Wireless Authentication slice execution count. */
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ADF_GEN4_TL_SL_EXEC_COUNTER(wat),
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/* Wireless Cipher slice execution count. */
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ADF_GEN4_TL_SL_EXEC_COUNTER(wcp),
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/* UCS slice execution count. */
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ADF_GEN4_TL_SL_EXEC_COUNTER(ucs),
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/* Cipher slice execution count. */
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ADF_GEN4_TL_SL_EXEC_COUNTER(cph),
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/* Authentication slice execution count. */
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ADF_GEN4_TL_SL_EXEC_COUNTER(ath),
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};
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/* Ring pair counters. */
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static const struct adf_tl_dbg_counter rp_counters[] = {
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/* PCIe partial transactions. */
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ADF_TL_COUNTER(PCI_TRANS_CNT_NAME, ADF_TL_SIMPLE_COUNT,
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ADF_GEN4_TL_RP_REG_OFF(reg_tl_pci_trans_cnt)),
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/* Get to put latency average[ns]. */
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ADF_TL_COUNTER_LATENCY(LAT_ACC_NAME, ADF_TL_COUNTER_NS_AVG,
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ADF_GEN4_TL_RP_REG_OFF(reg_tl_gp_lat_acc),
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ADF_GEN4_TL_RP_REG_OFF(reg_tl_ae_put_cnt)),
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/* PCIe write bandwidth[Mbps]. */
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ADF_TL_COUNTER(BW_IN_NAME, ADF_TL_COUNTER_MBPS,
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ADF_GEN4_TL_RP_REG_OFF(reg_tl_bw_in)),
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/* PCIe read bandwidth[Mbps]. */
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ADF_TL_COUNTER(BW_OUT_NAME, ADF_TL_COUNTER_MBPS,
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ADF_GEN4_TL_RP_REG_OFF(reg_tl_bw_out)),
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/* Message descriptor DevTLB hit rate. */
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ADF_TL_COUNTER(AT_GLOB_DTLB_HIT_NAME, ADF_TL_SIMPLE_COUNT,
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ADF_GEN4_TL_RP_REG_OFF(reg_tl_at_glob_devtlb_hit)),
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/* Message descriptor DevTLB miss rate. */
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ADF_TL_COUNTER(AT_GLOB_DTLB_MISS_NAME, ADF_TL_SIMPLE_COUNT,
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ADF_GEN4_TL_RP_REG_OFF(reg_tl_at_glob_devtlb_miss)),
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/* Payload DevTLB hit rate. */
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ADF_TL_COUNTER(AT_PAYLD_DTLB_HIT_NAME, ADF_TL_SIMPLE_COUNT,
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ADF_GEN4_TL_RP_REG_OFF(reg_tl_at_payld_devtlb_hit)),
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/* Payload DevTLB miss rate. */
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ADF_TL_COUNTER(AT_PAYLD_DTLB_MISS_NAME, ADF_TL_SIMPLE_COUNT,
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ADF_GEN4_TL_RP_REG_OFF(reg_tl_at_payld_devtlb_miss)),
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};
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void adf_gen4_init_tl_data(struct adf_tl_hw_data *tl_data)
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{
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tl_data->layout_sz = ADF_GEN4_TL_LAYOUT_SZ;
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tl_data->slice_reg_sz = ADF_GEN4_TL_SLICE_REG_SZ;
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tl_data->rp_reg_sz = ADF_GEN4_TL_RP_REG_SZ;
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tl_data->num_hbuff = ADF_GEN4_TL_NUM_HIST_BUFFS;
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tl_data->max_rp = ADF_GEN4_TL_MAX_RP_NUM;
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tl_data->msg_cnt_off = ADF_GEN4_TL_MSG_CNT_OFF;
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tl_data->cpp_ns_per_cycle = ADF_GEN4_CPP_NS_PER_CYCLE;
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tl_data->bw_units_to_bytes = ADF_GEN4_TL_BW_HW_UNITS_TO_BYTES;
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tl_data->dev_counters = dev_counters;
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tl_data->num_dev_counters = ARRAY_SIZE(dev_counters);
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tl_data->sl_util_counters = sl_util_counters;
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tl_data->sl_exec_counters = sl_exec_counters;
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tl_data->rp_counters = rp_counters;
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tl_data->num_rp_counters = ARRAY_SIZE(rp_counters);
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tl_data->max_sl_cnt = ADF_GEN4_TL_MAX_SLICES_PER_TYPE;
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}
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EXPORT_SYMBOL_GPL(adf_gen4_init_tl_data);
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