eb52707716
Expose through debugfs ring pair telemetry data for QAT GEN4 devices. This allows to gather metrics about the PCIe channel and device TLB for a selected ring pair. It is possible to monitor maximum 4 ring pairs at the time per device. For details, refer to debugfs-driver-qat_telemetry in Documentation/ABI. This patch is based on earlier work done by Wojciech Ziemba. Signed-off-by: Lucas Segarra Fernandez <lucas.segarra.fernandez@intel.com> Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Reviewed-by: Damian Muszynski <damian.muszynski@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
158 lines
6 KiB
C
158 lines
6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* Copyright (c) 2023 Intel Corporation. */
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#ifndef ADF_GEN4_TL_H
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#define ADF_GEN4_TL_H
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#include <linux/stddef.h>
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#include <linux/types.h>
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struct adf_tl_hw_data;
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/* Computation constants. */
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#define ADF_GEN4_CPP_NS_PER_CYCLE 2
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#define ADF_GEN4_TL_BW_HW_UNITS_TO_BYTES 64
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/* Maximum aggregation time. Value in milliseconds. */
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#define ADF_GEN4_TL_MAX_AGGR_TIME_MS 4000
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/* Num of buffers to store historic values. */
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#define ADF_GEN4_TL_NUM_HIST_BUFFS \
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(ADF_GEN4_TL_MAX_AGGR_TIME_MS / ADF_TL_DATA_WR_INTERVAL_MS)
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/* Max number of HW resources of one type. */
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#define ADF_GEN4_TL_MAX_SLICES_PER_TYPE 24
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/* Max number of simultaneously monitored ring pairs. */
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#define ADF_GEN4_TL_MAX_RP_NUM 4
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/**
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* struct adf_gen4_tl_slice_data_regs - HW slice data as populated by FW.
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* @reg_tm_slice_exec_cnt: Slice execution count.
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* @reg_tm_slice_util: Slice utilization.
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*/
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struct adf_gen4_tl_slice_data_regs {
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__u32 reg_tm_slice_exec_cnt;
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__u32 reg_tm_slice_util;
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};
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#define ADF_GEN4_TL_SLICE_REG_SZ sizeof(struct adf_gen4_tl_slice_data_regs)
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/**
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* struct adf_gen4_tl_device_data_regs - This structure stores device telemetry
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* counter values as are being populated periodically by device.
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* @reg_tl_rd_lat_acc: read latency accumulator
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* @reg_tl_gp_lat_acc: get-put latency accumulator
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* @reg_tl_at_page_req_lat_acc: AT/DevTLB page request latency accumulator
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* @reg_tl_at_trans_lat_acc: DevTLB transaction latency accumulator
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* @reg_tl_re_acc: accumulated ring empty time
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* @reg_tl_pci_trans_cnt: PCIe partial transactions
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* @reg_tl_rd_lat_max: maximum logged read latency
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* @reg_tl_rd_cmpl_cnt: read requests completed count
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* @reg_tl_gp_lat_max: maximum logged get to put latency
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* @reg_tl_ae_put_cnt: Accelerator Engine put counts across all rings
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* @reg_tl_bw_in: PCIe write bandwidth
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* @reg_tl_bw_out: PCIe read bandwidth
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* @reg_tl_at_page_req_cnt: DevTLB page requests count
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* @reg_tl_at_trans_lat_cnt: DevTLB transaction latency samples count
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* @reg_tl_at_max_tlb_used: maximum uTLB used
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* @reg_tl_re_cnt: ring empty time samples count
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* @reserved: reserved
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* @ath_slices: array of Authentication slices utilization registers
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* @cph_slices: array of Cipher slices utilization registers
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* @cpr_slices: array of Compression slices utilization registers
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* @xlt_slices: array of Translator slices utilization registers
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* @dcpr_slices: array of Decompression slices utilization registers
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* @pke_slices: array of PKE slices utilization registers
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* @ucs_slices: array of UCS slices utilization registers
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* @wat_slices: array of Wireless Authentication slices utilization registers
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* @wcp_slices: array of Wireless Cipher slices utilization registers
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*/
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struct adf_gen4_tl_device_data_regs {
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__u64 reg_tl_rd_lat_acc;
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__u64 reg_tl_gp_lat_acc;
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__u64 reg_tl_at_page_req_lat_acc;
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__u64 reg_tl_at_trans_lat_acc;
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__u64 reg_tl_re_acc;
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__u32 reg_tl_pci_trans_cnt;
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__u32 reg_tl_rd_lat_max;
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__u32 reg_tl_rd_cmpl_cnt;
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__u32 reg_tl_gp_lat_max;
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__u32 reg_tl_ae_put_cnt;
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__u32 reg_tl_bw_in;
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__u32 reg_tl_bw_out;
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__u32 reg_tl_at_page_req_cnt;
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__u32 reg_tl_at_trans_lat_cnt;
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__u32 reg_tl_at_max_tlb_used;
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__u32 reg_tl_re_cnt;
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__u32 reserved;
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struct adf_gen4_tl_slice_data_regs ath_slices[ADF_GEN4_TL_MAX_SLICES_PER_TYPE];
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struct adf_gen4_tl_slice_data_regs cph_slices[ADF_GEN4_TL_MAX_SLICES_PER_TYPE];
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struct adf_gen4_tl_slice_data_regs cpr_slices[ADF_GEN4_TL_MAX_SLICES_PER_TYPE];
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struct adf_gen4_tl_slice_data_regs xlt_slices[ADF_GEN4_TL_MAX_SLICES_PER_TYPE];
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struct adf_gen4_tl_slice_data_regs dcpr_slices[ADF_GEN4_TL_MAX_SLICES_PER_TYPE];
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struct adf_gen4_tl_slice_data_regs pke_slices[ADF_GEN4_TL_MAX_SLICES_PER_TYPE];
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struct adf_gen4_tl_slice_data_regs ucs_slices[ADF_GEN4_TL_MAX_SLICES_PER_TYPE];
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struct adf_gen4_tl_slice_data_regs wat_slices[ADF_GEN4_TL_MAX_SLICES_PER_TYPE];
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struct adf_gen4_tl_slice_data_regs wcp_slices[ADF_GEN4_TL_MAX_SLICES_PER_TYPE];
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};
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/**
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* struct adf_gen4_tl_ring_pair_data_regs - This structure stores Ring Pair
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* telemetry counter values as are being populated periodically by device.
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* @reg_tl_gp_lat_acc: get-put latency accumulator
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* @reserved: reserved
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* @reg_tl_pci_trans_cnt: PCIe partial transactions
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* @reg_tl_ae_put_cnt: Accelerator Engine put counts across all rings
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* @reg_tl_bw_in: PCIe write bandwidth
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* @reg_tl_bw_out: PCIe read bandwidth
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* @reg_tl_at_glob_devtlb_hit: Message descriptor DevTLB hit rate
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* @reg_tl_at_glob_devtlb_miss: Message descriptor DevTLB miss rate
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* @reg_tl_at_payld_devtlb_hit: Payload DevTLB hit rate
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* @reg_tl_at_payld_devtlb_miss: Payload DevTLB miss rate
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* @reg_tl_re_cnt: ring empty time samples count
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* @reserved1: reserved
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*/
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struct adf_gen4_tl_ring_pair_data_regs {
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__u64 reg_tl_gp_lat_acc;
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__u64 reserved;
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__u32 reg_tl_pci_trans_cnt;
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__u32 reg_tl_ae_put_cnt;
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__u32 reg_tl_bw_in;
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__u32 reg_tl_bw_out;
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__u32 reg_tl_at_glob_devtlb_hit;
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__u32 reg_tl_at_glob_devtlb_miss;
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__u32 reg_tl_at_payld_devtlb_hit;
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__u32 reg_tl_at_payld_devtlb_miss;
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__u32 reg_tl_re_cnt;
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__u32 reserved1;
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};
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#define ADF_GEN4_TL_RP_REG_SZ sizeof(struct adf_gen4_tl_ring_pair_data_regs)
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/**
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* struct adf_gen4_tl_layout - This structure represents entire telemetry
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* counters data: Device + 4 Ring Pairs as are being populated periodically
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* by device.
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* @tl_device_data_regs: structure of device telemetry registers
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* @tl_ring_pairs_data_regs: array of ring pairs telemetry registers
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* @reg_tl_msg_cnt: telemetry messages counter
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* @reserved: reserved
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*/
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struct adf_gen4_tl_layout {
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struct adf_gen4_tl_device_data_regs tl_device_data_regs;
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struct adf_gen4_tl_ring_pair_data_regs
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tl_ring_pairs_data_regs[ADF_GEN4_TL_MAX_RP_NUM];
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__u32 reg_tl_msg_cnt;
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__u32 reserved;
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};
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#define ADF_GEN4_TL_LAYOUT_SZ sizeof(struct adf_gen4_tl_layout)
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#define ADF_GEN4_TL_MSG_CNT_OFF offsetof(struct adf_gen4_tl_layout, reg_tl_msg_cnt)
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#ifdef CONFIG_DEBUG_FS
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void adf_gen4_init_tl_data(struct adf_tl_hw_data *tl_data);
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#else
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static inline void adf_gen4_init_tl_data(struct adf_tl_hw_data *tl_data)
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{
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}
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#endif /* CONFIG_DEBUG_FS */
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#endif /* ADF_GEN4_TL_H */
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