e2b67859ab
Add a mechanism that allows to inject a heartbeat error for testing purposes. A new attribute `inject_error` is added to debugfs for each QAT device. Upon a write on this attribute, the driver will inject an error on the device which can then be detected by the heartbeat feature. Errors are breaking the device functionality thus they require a device reset in order to be recovered. This functionality is not compiled by default, to enable it CRYPTO_DEV_QAT_ERROR_INJECTION must be set. Signed-off-by: Damian Muszynski <damian.muszynski@intel.com> Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Reviewed-by: Lucas Segarra Fernandez <lucas.segarra.fernandez@intel.com> Reviewed-by: Ahsan Atta <ahsan.atta@intel.com> Reviewed-by: Markas Rapoportas <markas.rapoportas@intel.com> Signed-off-by: Mun Chun Yep <mun.chun.yep@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
130 lines
3.9 KiB
C
130 lines
3.9 KiB
C
// SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only)
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/* Copyright(c) 2014 - 2020 Intel Corporation */
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#include "adf_accel_devices.h"
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#include "adf_common_drv.h"
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#include "adf_transport_internal.h"
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#define ADF_ARB_NUM 4
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#define ADF_ARB_REG_SIZE 0x4
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#define WRITE_CSR_ARB_SARCONFIG(csr_addr, arb_offset, index, value) \
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ADF_CSR_WR(csr_addr, (arb_offset) + \
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(ADF_ARB_REG_SIZE * (index)), value)
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#define WRITE_CSR_ARB_WT2SAM(csr_addr, arb_offset, wt_offset, index, value) \
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ADF_CSR_WR(csr_addr, ((arb_offset) + (wt_offset)) + \
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(ADF_ARB_REG_SIZE * (index)), value)
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int adf_init_arb(struct adf_accel_dev *accel_dev)
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{
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struct adf_hw_device_data *hw_data = accel_dev->hw_device;
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void __iomem *csr = accel_dev->transport->banks[0].csr_addr;
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unsigned long ae_mask = hw_data->ae_mask;
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u32 arb_off, wt_off, arb_cfg;
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const u32 *thd_2_arb_cfg;
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struct arb_info info;
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int arb, i;
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hw_data->get_arb_info(&info);
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arb_cfg = info.arb_cfg;
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arb_off = info.arb_offset;
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wt_off = info.wt2sam_offset;
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/* Service arb configured for 32 bytes responses and
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* ring flow control check enabled. */
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for (arb = 0; arb < ADF_ARB_NUM; arb++)
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WRITE_CSR_ARB_SARCONFIG(csr, arb_off, arb, arb_cfg);
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/* Map worker threads to service arbiters */
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thd_2_arb_cfg = hw_data->get_arb_mapping(accel_dev);
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for_each_set_bit(i, &ae_mask, hw_data->num_engines)
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WRITE_CSR_ARB_WT2SAM(csr, arb_off, wt_off, i, thd_2_arb_cfg[i]);
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return 0;
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}
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EXPORT_SYMBOL_GPL(adf_init_arb);
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void adf_update_ring_arb(struct adf_etr_ring_data *ring)
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{
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struct adf_accel_dev *accel_dev = ring->bank->accel_dev;
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struct adf_hw_device_data *hw_data = accel_dev->hw_device;
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struct adf_hw_csr_ops *csr_ops = GET_CSR_OPS(accel_dev);
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u32 tx_ring_mask = hw_data->tx_rings_mask;
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u32 shift = hw_data->tx_rx_gap;
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u32 arben, arben_tx, arben_rx;
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u32 rx_ring_mask;
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/*
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* Enable arbitration on a ring only if the TX half of the ring mask
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* matches the RX part. This results in writes to CSR on both TX and
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* RX update - only one is necessary, but both are done for
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* simplicity.
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*/
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rx_ring_mask = tx_ring_mask << shift;
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arben_tx = (ring->bank->ring_mask & tx_ring_mask) >> 0;
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arben_rx = (ring->bank->ring_mask & rx_ring_mask) >> shift;
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arben = arben_tx & arben_rx;
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csr_ops->write_csr_ring_srv_arb_en(ring->bank->csr_addr,
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ring->bank->bank_number, arben);
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}
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void adf_exit_arb(struct adf_accel_dev *accel_dev)
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{
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struct adf_hw_device_data *hw_data = accel_dev->hw_device;
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struct adf_hw_csr_ops *csr_ops = GET_CSR_OPS(accel_dev);
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u32 arb_off, wt_off;
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struct arb_info info;
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void __iomem *csr;
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unsigned int i;
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hw_data->get_arb_info(&info);
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arb_off = info.arb_offset;
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wt_off = info.wt2sam_offset;
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if (!accel_dev->transport)
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return;
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csr = accel_dev->transport->banks[0].csr_addr;
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hw_data->get_arb_info(&info);
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/* Reset arbiter configuration */
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for (i = 0; i < ADF_ARB_NUM; i++)
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WRITE_CSR_ARB_SARCONFIG(csr, arb_off, i, 0);
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/* Unmap worker threads to service arbiters */
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for (i = 0; i < hw_data->num_engines; i++)
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WRITE_CSR_ARB_WT2SAM(csr, arb_off, wt_off, i, 0);
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/* Disable arbitration on all rings */
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for (i = 0; i < GET_MAX_BANKS(accel_dev); i++)
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csr_ops->write_csr_ring_srv_arb_en(csr, i, 0);
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}
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EXPORT_SYMBOL_GPL(adf_exit_arb);
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int adf_disable_arb_thd(struct adf_accel_dev *accel_dev, u32 ae, u32 thr)
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{
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void __iomem *csr = accel_dev->transport->banks[0].csr_addr;
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struct adf_hw_device_data *hw_data = accel_dev->hw_device;
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const u32 *thd_2_arb_cfg;
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struct arb_info info;
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u32 ae_thr_map;
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if (ADF_AE_STRAND0_THREAD == thr || ADF_AE_STRAND1_THREAD == thr)
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thr = ADF_AE_ADMIN_THREAD;
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hw_data->get_arb_info(&info);
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thd_2_arb_cfg = hw_data->get_arb_mapping(accel_dev);
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if (!thd_2_arb_cfg)
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return -EFAULT;
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/* Disable scheduling for this particular AE and thread */
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ae_thr_map = *(thd_2_arb_cfg + ae);
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ae_thr_map &= ~(GENMASK(3, 0) << (thr * BIT(2)));
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WRITE_CSR_ARB_WT2SAM(csr, info.arb_offset, info.wt2sam_offset, ae,
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ae_thr_map);
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return 0;
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}
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