483fd65ce2
The function adf_send_admin_tl_start() enables the telemetry (TL)
feature on a QAT device by sending the ICP_QAT_FW_TL_START message to
the firmware. This triggers the FW to start writing TL data to a DMA
buffer in memory and returns an array containing the number of
accelerators of each type (slices) supported by this HW.
The pointer to this array is stored in the adf_tl_hw_data data
structure called slice_cnt.
The array slice_cnt is then used in the function tl_print_dev_data()
to report in debugfs only statistics about the supported accelerators.
An incorrect value of the elements in slice_cnt might lead to an out
of bounds memory read.
At the moment, there isn't an implementation of FW that returns a wrong
value, but for robustness validate the slice count array returned by FW.
Fixes: 69e7649f7c ("crypto: qat - add support for device telemetry")
Signed-off-by: Lucas Segarra Fernandez <lucas.segarra.fernandez@intel.com>
Reviewed-by: Damian Muszynski <damian.muszynski@intel.com>
Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
100 lines
2.6 KiB
C
100 lines
2.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* Copyright (c) 2023 Intel Corporation. */
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#ifndef ADF_TELEMETRY_H
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#define ADF_TELEMETRY_H
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#include <linux/bits.h>
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#include <linux/mutex.h>
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#include <linux/types.h>
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#include <linux/workqueue.h>
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#include "icp_qat_fw_init_admin.h"
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struct adf_accel_dev;
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struct adf_tl_dbg_counter;
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struct dentry;
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#define ADF_TL_SL_CNT_COUNT \
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(sizeof(struct icp_qat_fw_init_admin_slice_cnt) / sizeof(__u8))
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#define TL_CAPABILITY_BIT BIT(1)
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/* Interval within device writes data to DMA region. Value in milliseconds. */
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#define ADF_TL_DATA_WR_INTERVAL_MS 1000
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/* Interval within timer interrupt should be handled. Value in milliseconds. */
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#define ADF_TL_TIMER_INT_MS (ADF_TL_DATA_WR_INTERVAL_MS / 2)
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#define ADF_TL_RP_REGS_DISABLED (0xff)
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struct adf_tl_hw_data {
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size_t layout_sz;
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size_t slice_reg_sz;
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size_t rp_reg_sz;
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size_t msg_cnt_off;
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const struct adf_tl_dbg_counter *dev_counters;
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const struct adf_tl_dbg_counter *sl_util_counters;
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const struct adf_tl_dbg_counter *sl_exec_counters;
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const struct adf_tl_dbg_counter *rp_counters;
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u8 num_hbuff;
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u8 cpp_ns_per_cycle;
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u8 bw_units_to_bytes;
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u8 num_dev_counters;
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u8 num_rp_counters;
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u8 max_rp;
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u8 max_sl_cnt;
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};
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struct adf_telemetry {
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struct adf_accel_dev *accel_dev;
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atomic_t state;
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u32 hbuffs;
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int hb_num;
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u32 msg_cnt;
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dma_addr_t regs_data_p; /* bus address for DMA mapping */
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void *regs_data; /* virtual address for DMA mapping */
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/**
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* @regs_hist_buff: array of pointers to copies of the last @hbuffs
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* values of @regs_data
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*/
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void **regs_hist_buff;
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struct dentry *dbg_dir;
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u8 *rp_num_indexes;
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/**
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* @regs_hist_lock: protects from race conditions between write and read
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* to the copies referenced by @regs_hist_buff
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*/
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struct mutex regs_hist_lock;
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/**
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* @wr_lock: protects from concurrent writes to debugfs telemetry files
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*/
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struct mutex wr_lock;
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struct delayed_work work_ctx;
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struct icp_qat_fw_init_admin_slice_cnt slice_cnt;
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};
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#ifdef CONFIG_DEBUG_FS
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int adf_tl_init(struct adf_accel_dev *accel_dev);
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int adf_tl_start(struct adf_accel_dev *accel_dev);
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void adf_tl_stop(struct adf_accel_dev *accel_dev);
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void adf_tl_shutdown(struct adf_accel_dev *accel_dev);
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int adf_tl_run(struct adf_accel_dev *accel_dev, int state);
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int adf_tl_halt(struct adf_accel_dev *accel_dev);
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#else
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static inline int adf_tl_init(struct adf_accel_dev *accel_dev)
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{
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return 0;
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}
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static inline int adf_tl_start(struct adf_accel_dev *accel_dev)
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{
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return 0;
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}
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static inline void adf_tl_stop(struct adf_accel_dev *accel_dev)
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{
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}
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static inline void adf_tl_shutdown(struct adf_accel_dev *accel_dev)
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{
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}
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#endif /* CONFIG_DEBUG_FS */
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#endif /* ADF_TELEMETRY_H */
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