9299cde973
Problem is that on some platforms, we do get QGV point mask in wrong
state on boot. However driver assumes it is set to 0
(i.e all points allowed), however in reality we might get them all
restricted, causing issues.
Lets disable SAGV initially to force proper QGV point state.
If more QGV points are available, driver will recalculate and update
those then after next commit.
v2: - Added trace to see which QGV/PSF GV point is used when SAGV is
disabled.
v3: - Move force disable function to intel_bw_init in order to initialize
bw state as well, so that hw/sw are immediately in sync after init.
v4: - Don't try sending PCode request, seems like it is not possible at
intel_bw_init, however assigning bw->state to be restricted as if
SAGV is off, still forces driveer to send PCode request anyway on
next modeset, so the solution still works.
However we still need to address the case, when no display is
connected, which anyway requires much more changes.
v5: - Put PCode request back and apply temporary hack to make the
request succeed(in case if there 2 PSF GV points with same BW, PCode
accepts only if both points are restricted/unrestricted same time)
- Fix argument sequence for adl_qgv_bw(Ville Syrjälä)
v6: - Fix wrong platform checks, not to break everything else.
v7: - Split the handling of quplicate QGV/PSF GV points (Vinod)
Restrict force disable to display version below 14 (Vinod)
v8: - Simplify icl_force_disable_sagv (Vinod)
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240405113533.338553-5-vinod.govindapillai@intel.com
89 lines
3 KiB
C
89 lines
3 KiB
C
/* SPDX-License-Identifier: MIT */
|
|
/*
|
|
* Copyright © 2022 Intel Corporation
|
|
*/
|
|
|
|
#ifndef __SKL_WATERMARK_H__
|
|
#define __SKL_WATERMARK_H__
|
|
|
|
#include <linux/types.h>
|
|
|
|
#include "intel_display_limits.h"
|
|
#include "intel_global_state.h"
|
|
#include "intel_wm_types.h"
|
|
|
|
struct drm_i915_private;
|
|
struct intel_atomic_state;
|
|
struct intel_bw_state;
|
|
struct intel_crtc;
|
|
struct intel_crtc_state;
|
|
struct intel_plane;
|
|
|
|
u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *i915);
|
|
|
|
void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
|
|
void intel_sagv_post_plane_update(struct intel_atomic_state *state);
|
|
bool intel_can_enable_sagv(struct drm_i915_private *i915,
|
|
const struct intel_bw_state *bw_state);
|
|
bool intel_has_sagv(struct drm_i915_private *i915);
|
|
|
|
u32 skl_ddb_dbuf_slice_mask(struct drm_i915_private *i915,
|
|
const struct skl_ddb_entry *entry);
|
|
|
|
void skl_write_plane_wm(struct intel_plane *plane,
|
|
const struct intel_crtc_state *crtc_state);
|
|
void skl_write_cursor_wm(struct intel_plane *plane,
|
|
const struct intel_crtc_state *crtc_state);
|
|
|
|
bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
|
|
const struct skl_ddb_entry *entries,
|
|
int num_entries, int ignore_idx);
|
|
|
|
void intel_wm_state_verify(struct intel_atomic_state *state,
|
|
struct intel_crtc *crtc);
|
|
|
|
void skl_watermark_ipc_init(struct drm_i915_private *i915);
|
|
void skl_watermark_ipc_update(struct drm_i915_private *i915);
|
|
bool skl_watermark_ipc_enabled(struct drm_i915_private *i915);
|
|
void skl_watermark_debugfs_register(struct drm_i915_private *i915);
|
|
|
|
unsigned int skl_watermark_max_latency(struct drm_i915_private *i915,
|
|
int initial_wm_level);
|
|
void skl_wm_init(struct drm_i915_private *i915);
|
|
|
|
struct intel_dbuf_state {
|
|
struct intel_global_state base;
|
|
|
|
struct skl_ddb_entry ddb[I915_MAX_PIPES];
|
|
unsigned int weight[I915_MAX_PIPES];
|
|
u8 slices[I915_MAX_PIPES];
|
|
u8 enabled_slices;
|
|
u8 active_pipes;
|
|
u8 mdclk_cdclk_ratio;
|
|
bool joined_mbus;
|
|
};
|
|
|
|
struct intel_dbuf_state *
|
|
intel_atomic_get_dbuf_state(struct intel_atomic_state *state);
|
|
|
|
#define to_intel_dbuf_state(global_state) \
|
|
container_of_const((global_state), struct intel_dbuf_state, base)
|
|
|
|
#define intel_atomic_get_old_dbuf_state(state) \
|
|
to_intel_dbuf_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->display.dbuf.obj))
|
|
#define intel_atomic_get_new_dbuf_state(state) \
|
|
to_intel_dbuf_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->display.dbuf.obj))
|
|
|
|
int intel_dbuf_init(struct drm_i915_private *i915);
|
|
int intel_dbuf_state_set_mdclk_cdclk_ratio(struct intel_atomic_state *state,
|
|
int ratio);
|
|
|
|
void intel_dbuf_pre_plane_update(struct intel_atomic_state *state);
|
|
void intel_dbuf_post_plane_update(struct intel_atomic_state *state);
|
|
void intel_dbuf_mdclk_cdclk_ratio_update(struct drm_i915_private *i915,
|
|
int ratio, bool joined_mbus);
|
|
void intel_dbuf_mbus_pre_ddb_update(struct intel_atomic_state *state);
|
|
void intel_dbuf_mbus_post_ddb_update(struct intel_atomic_state *state);
|
|
|
|
#endif /* __SKL_WATERMARK_H__ */
|
|
|