51c1b42a23
We missed setting the CCS mode during resume and engine resets. Create a workaround to be added in the engine's workaround list. This workaround sets the XEHP_CCS_MODE value at every reset. The issue can be reproduced by running: $ clpeak --kernel-latency Without resetting the CCS mode, we encounter a fence timeout: Fence expiration time out i915-0000:03:00.0:clpeak[2387]:2! Fixes:6db31251bb("drm/i915/gt: Enable only one CCS for compute workload") Reported-by: Gnattu OC <gnattuoc@me.com> Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10895 Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> Cc: Chris Wilson <chris.p.wilson@linux.intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: <stable@vger.kernel.org> # v6.2+ Tested-by: Gnattu OC <gnattuoc@me.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Tested-by: Krzysztof Gibala <krzysztof.gibala@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240426000723.229296-1-andi.shyti@linux.intel.com (cherry picked from commit4cfca03f76) Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
39 lines
835 B
C
39 lines
835 B
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2024 Intel Corporation
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*/
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#include "i915_drv.h"
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#include "intel_gt.h"
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#include "intel_gt_ccs_mode.h"
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#include "intel_gt_regs.h"
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unsigned int intel_gt_apply_ccs_mode(struct intel_gt *gt)
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{
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int cslice;
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u32 mode = 0;
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int first_ccs = __ffs(CCS_MASK(gt));
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if (!IS_DG2(gt->i915))
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return 0;
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/* Build the value for the fixed CCS load balancing */
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for (cslice = 0; cslice < I915_MAX_CCS; cslice++) {
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if (CCS_MASK(gt) & BIT(cslice))
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/*
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* If available, assign the cslice
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* to the first available engine...
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*/
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mode |= XEHP_CCS_MODE_CSLICE(cslice, first_ccs);
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else
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/*
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* ... otherwise, mark the cslice as
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* unavailable if no CCS dispatches here
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*/
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mode |= XEHP_CCS_MODE_CSLICE(cslice,
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XEHP_CCS_MODE_CSLICE_MASK);
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}
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return mode;
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}
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