31cc65b4c7
The GSC notifies us of a proxy request via the HECI2 interrupt. The interrupt must be enabled both in the HECI layer and in our usual gt irq programming; for the latter, the interrupt is enabled via the same enable register as the GSC CS, but it does have its own mask register. When the interrupt is received, we also need to de-assert it in both layers. The handling of the proxy request is deferred to the same worker that we use for GSC load. New flags have been added to distinguish between the init case and the proxy interrupt. v2: Make sure not to set the reset bit when enabling/disabling the GSC interrupts, fix defines (Alan) v3: rebase on proxy status register check Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Alan Previn <alan.previn.teres.alexis@intel.com> Reviewed-by: Alan Previn <alan.previn.teres.alexis@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230502163854.317653-5-daniele.ceraolospurio@intel.com
18 lines
432 B
C
18 lines
432 B
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2023 Intel Corporation
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*/
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#ifndef _INTEL_GSC_PROXY_H_
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#define _INTEL_GSC_PROXY_H_
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#include <linux/types.h>
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struct intel_gsc_uc;
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int intel_gsc_proxy_init(struct intel_gsc_uc *gsc);
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void intel_gsc_proxy_fini(struct intel_gsc_uc *gsc);
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int intel_gsc_proxy_request_handler(struct intel_gsc_uc *gsc);
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void intel_gsc_proxy_irq_handler(struct intel_gsc_uc *gsc, u32 iir);
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#endif
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