561055b810
Add a new debugfs to dump information about the GSC. This includes: - the FW path and SW tracking status; - the release, security and compatibility versions; - the HECI1 status registers. Note that those are the same registers that the mei driver dumps in their own status sysfs on DG2 (where mei owns the GSC). To make it simpler to loop through the status register, the code has been update to use a PICK macro and the existing code using the regs had been adapted to match. v2: fix includes and copyright dates (Alan) v3: actually fix the includes Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Alan Previn <alan.previn.teres.alexis@intel.com> Cc: John Harrison <John.C.Harrison@Intel.com> Reviewed-by: Alan Previn <alan.previn.teres.alexis@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230612181529.2222451-5-daniele.ceraolospurio@intel.com
85 lines
2.5 KiB
C
85 lines
2.5 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2022 Intel Corporation
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*/
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#ifndef _INTEL_GSC_UC_H_
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#define _INTEL_GSC_UC_H_
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#include "intel_uc_fw.h"
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struct drm_printer;
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struct i915_vma;
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struct intel_context;
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struct i915_gsc_proxy_component;
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struct intel_gsc_uc {
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/* Generic uC firmware management */
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struct intel_uc_fw fw;
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/* GSC-specific additions */
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/*
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* The GSC has 3 version numbers:
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* - Release version (incremented with each build)
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* - Security version (incremented on security fix)
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* - Compatibility version (incremented on interface change)
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*
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* The one we care about to use the binary is the last one, so that's
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* the one we save inside the intel_uc_fw structure. The other two
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* versions are only used for debug/info purposes, so we save them here.
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*
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* Note that the release and security versions are available in the
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* binary header, while the compatibility version must be queried after
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* loading the binary.
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*/
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struct intel_uc_fw_ver release;
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u32 security_version;
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struct i915_vma *local; /* private memory for GSC usage */
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void __iomem *local_vaddr; /* pointer to access the private memory */
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struct intel_context *ce; /* for submission to GSC FW via GSC engine */
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/* for delayed load and proxy handling */
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struct workqueue_struct *wq;
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struct work_struct work;
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u32 gsc_work_actions; /* protected by gt->irq_lock */
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#define GSC_ACTION_FW_LOAD BIT(0)
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#define GSC_ACTION_SW_PROXY BIT(1)
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struct {
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struct i915_gsc_proxy_component *component;
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bool component_added;
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struct i915_vma *vma;
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void *to_gsc;
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void *to_csme;
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struct mutex mutex; /* protects the tee channel binding */
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} proxy;
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};
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void intel_gsc_uc_init_early(struct intel_gsc_uc *gsc);
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int intel_gsc_uc_init(struct intel_gsc_uc *gsc);
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void intel_gsc_uc_fini(struct intel_gsc_uc *gsc);
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void intel_gsc_uc_suspend(struct intel_gsc_uc *gsc);
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void intel_gsc_uc_resume(struct intel_gsc_uc *gsc);
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void intel_gsc_uc_flush_work(struct intel_gsc_uc *gsc);
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void intel_gsc_uc_load_start(struct intel_gsc_uc *gsc);
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void intel_gsc_uc_load_status(struct intel_gsc_uc *gsc, struct drm_printer *p);
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static inline bool intel_gsc_uc_is_supported(struct intel_gsc_uc *gsc)
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{
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return intel_uc_fw_is_supported(&gsc->fw);
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}
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static inline bool intel_gsc_uc_is_wanted(struct intel_gsc_uc *gsc)
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{
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return intel_uc_fw_is_enabled(&gsc->fw);
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}
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static inline bool intel_gsc_uc_is_used(struct intel_gsc_uc *gsc)
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{
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GEM_BUG_ON(__intel_uc_fw_status(&gsc->fw) == INTEL_UC_FIRMWARE_SELECTED);
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return intel_uc_fw_is_available(&gsc->fw);
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}
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#endif
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