44e694958b
As for display, the intent is to share the display code with the i915 driver so that there is maximum reuse there. We do this by recompiling i915/display code twice. Now that i915 has been adapted to support the Xe build, we can add the xe/display support. This initial work is a collaboration of many people and unfortunately this squashed patch won't fully honor the proper credits. But let's try to add a few from the squashed patches: Co-developed-by: Matthew Brost <matthew.brost@intel.com> Co-developed-by: Jani Nikula <jani.nikula@intel.com> Co-developed-by: Lucas De Marchi <lucas.demarchi@intel.com> Co-developed-by: Matt Roper <matthew.d.roper@intel.com> Co-developed-by: Mauro Carvalho Chehab <mchehab@kernel.org> Co-developed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Co-developed-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
77 lines
2.2 KiB
C
77 lines
2.2 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2023 Intel Corporation
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*/
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#include "i915_drv.h"
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#include "i915_irq.h"
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#include "i915_reg.h"
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#include "intel_uncore.h"
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void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
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i915_reg_t iir, i915_reg_t ier)
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{
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intel_uncore_write(uncore, imr, 0xffffffff);
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intel_uncore_posting_read(uncore, imr);
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intel_uncore_write(uncore, ier, 0);
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/* IIR can theoretically queue up two events. Be paranoid. */
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intel_uncore_write(uncore, iir, 0xffffffff);
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intel_uncore_posting_read(uncore, iir);
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intel_uncore_write(uncore, iir, 0xffffffff);
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intel_uncore_posting_read(uncore, iir);
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}
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/*
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* We should clear IMR at preinstall/uninstall, and just check at postinstall.
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*/
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void gen3_assert_iir_is_zero(struct intel_uncore *uncore, i915_reg_t reg)
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{
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struct xe_device *xe = container_of(uncore, struct xe_device, uncore);
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u32 val = intel_uncore_read(uncore, reg);
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if (val == 0)
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return;
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drm_WARN(&xe->drm, 1,
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"Interrupt register 0x%x is not zero: 0x%08x\n",
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i915_mmio_reg_offset(reg), val);
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intel_uncore_write(uncore, reg, 0xffffffff);
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intel_uncore_posting_read(uncore, reg);
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intel_uncore_write(uncore, reg, 0xffffffff);
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intel_uncore_posting_read(uncore, reg);
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}
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void gen3_irq_init(struct intel_uncore *uncore,
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i915_reg_t imr, u32 imr_val,
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i915_reg_t ier, u32 ier_val,
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i915_reg_t iir)
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{
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gen3_assert_iir_is_zero(uncore, iir);
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intel_uncore_write(uncore, ier, ier_val);
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intel_uncore_write(uncore, imr, imr_val);
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intel_uncore_posting_read(uncore, imr);
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}
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bool intel_irqs_enabled(struct xe_device *xe)
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{
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/*
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* XXX: i915 has a racy handling of the irq.enabled, since it doesn't
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* lock its transitions. Because of that, the irq.enabled sometimes
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* is not read with the irq.lock in place.
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* However, the most critical cases like vblank and page flips are
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* properly using the locks.
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* We cannot take the lock in here or run any kind of assert because
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* of i915 inconsistency.
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* But at this point the xe irq is better protected against races,
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* although the full solution would be protecting the i915 side.
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*/
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return xe->irq.enabled;
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}
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void intel_synchronize_irq(struct xe_device *xe)
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{
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synchronize_irq(to_pci_dev(xe->drm.dev)->irq);
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}
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