62742d1266
The flags stored in the BO grew over time without following much a naming pattern. First of all, get rid of the _BIT suffix that was banned from everywhere else due to the guideline in drivers/gpu/drm/i915/i915_reg.h that xe kind of follows: Define bits using ``REG_BIT(N)``. Do **not** add ``_BIT`` suffix to the name. Here the flags aren't for a register, but it's good practice to keep it consistent. Second divergence on names is the use or not of "CREATE". This is because most of the flags are passed to xe_bo_create*() family of functions, changing its behavior. However, since the flags are also stored in the bo itself and checked elsewhere in the code, it seems better to just omit the CREATE part. With those 2 guidelines, all the flags are given the form XE_BO_FLAG_<FLAG_NAME> with the following commands: git grep -le "XE_BO_" -- drivers/gpu/drm/xe | xargs sed -i \ -e "s/XE_BO_\([_A-Z0-9]*\)_BIT/XE_BO_\1/g" \ -e 's/XE_BO_CREATE_/XE_BO_FLAG_/g' git grep -le "XE_BO_" -- drivers/gpu/drm/xe | xargs sed -i -r \ -e 's/XE_BO_(DEFER_BACKING|SCANOUT|FIXED_PLACEMENT|PAGETABLE|NEEDS_CPU_ACCESS|NEEDS_UC|INTERNAL_TEST|INTERNAL_64K|GGTT_INVALIDATE)/XE_BO_FLAG_\1/g' And then the defines in drivers/gpu/drm/xe/xe_bo.h are adjusted to follow the coding style. Reviewed-by: Matthew Auld <matthew.auld@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240322142702.186529-3-lucas.demarchi@intel.com Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
71 lines
1.7 KiB
C
71 lines
1.7 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright 2023, Intel Corporation.
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*/
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#include "i915_drv.h"
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#include "i915_vma.h"
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#include "intel_display_types.h"
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#include "intel_dsb_buffer.h"
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#include "xe_bo.h"
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#include "xe_gt.h"
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u32 intel_dsb_buffer_ggtt_offset(struct intel_dsb_buffer *dsb_buf)
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{
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return xe_bo_ggtt_addr(dsb_buf->vma->bo);
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}
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void intel_dsb_buffer_write(struct intel_dsb_buffer *dsb_buf, u32 idx, u32 val)
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{
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iosys_map_wr(&dsb_buf->vma->bo->vmap, idx * 4, u32, val);
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}
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u32 intel_dsb_buffer_read(struct intel_dsb_buffer *dsb_buf, u32 idx)
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{
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return iosys_map_rd(&dsb_buf->vma->bo->vmap, idx * 4, u32);
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}
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void intel_dsb_buffer_memset(struct intel_dsb_buffer *dsb_buf, u32 idx, u32 val, size_t size)
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{
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WARN_ON(idx > (dsb_buf->buf_size - size) / sizeof(*dsb_buf->cmd_buf));
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iosys_map_memset(&dsb_buf->vma->bo->vmap, idx * 4, val, size);
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}
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bool intel_dsb_buffer_create(struct intel_crtc *crtc, struct intel_dsb_buffer *dsb_buf, size_t size)
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{
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struct drm_i915_private *i915 = to_i915(crtc->base.dev);
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struct drm_i915_gem_object *obj;
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struct i915_vma *vma;
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vma = kzalloc(sizeof(*vma), GFP_KERNEL);
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if (!vma)
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return false;
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obj = xe_bo_create_pin_map(i915, xe_device_get_root_tile(i915),
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NULL, PAGE_ALIGN(size),
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ttm_bo_type_kernel,
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XE_BO_FLAG_VRAM_IF_DGFX(xe_device_get_root_tile(i915)) |
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XE_BO_FLAG_GGTT);
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if (IS_ERR(obj)) {
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kfree(vma);
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return false;
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}
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vma->bo = obj;
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dsb_buf->vma = vma;
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dsb_buf->buf_size = size;
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return true;
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}
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void intel_dsb_buffer_cleanup(struct intel_dsb_buffer *dsb_buf)
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{
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xe_bo_unpin_map_no_vm(dsb_buf->vma->bo);
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kfree(dsb_buf->vma);
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}
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void intel_dsb_buffer_flush_map(struct intel_dsb_buffer *dsb_buf)
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{
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/* TODO: add xe specific flush_map() for dsb buffer object. */
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}
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