b9b7db4908
The LRCs on some of our newer platforms appear to contain a few GPU instructions that weren't handled in our LRC parser. Add the relevant instruction names and opcodes so that our debugfs LRC dumps will properly indicate what these are. Bspec: 55866, 64848, 46931 Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240222184009.6857-2-matthew.d.roper@intel.com
34 lines
1.2 KiB
C
34 lines
1.2 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2023 Intel Corporation
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*/
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#ifndef _XE_INSTR_DEFS_H_
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#define _XE_INSTR_DEFS_H_
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#include "regs/xe_reg_defs.h"
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/*
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* The first dword of any GPU instruction is the "instruction header." Bits
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* 31:29 identify the general type of the command and determine how exact
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* opcodes and sub-opcodes will be encoded in the remaining bits.
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*/
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#define XE_INSTR_CMD_TYPE GENMASK(31, 29)
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#define XE_INSTR_MI REG_FIELD_PREP(XE_INSTR_CMD_TYPE, 0x0)
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#define XE_INSTR_GSC REG_FIELD_PREP(XE_INSTR_CMD_TYPE, 0x2)
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#define XE_INSTR_GFXPIPE REG_FIELD_PREP(XE_INSTR_CMD_TYPE, 0x3)
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#define XE_INSTR_GFX_STATE REG_FIELD_PREP(XE_INSTR_CMD_TYPE, 0x4)
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/*
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* Most (but not all) instructions have a "length" field in the instruction
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* header. The value expected is the total number of dwords for the
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* instruction, minus two.
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*
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* Some instructions have length fields longer or shorter than 8 bits, but
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* those are rare. This definition can be used for the common case where
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* the length field is from 7:0.
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*/
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#define XE_INSTR_LEN_MASK GENMASK(7, 0)
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#define XE_INSTR_NUM_DW(x) REG_FIELD_PREP(XE_INSTR_LEN_MASK, (x) - 2)
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#endif
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