ee3b1e31d5
The q->width should always be exactly one here for migration queue/vm. The width will anyway be overridden later since we need to emit two jumps for special migration jobs. Enforce that here to ensure caller is not doing something strange. While here also convert to the helper to determine if the queue is migration based. Signed-off-by: Matthew Auld <matthew.auld@intel.com> Cc: Nirmoy Das <nirmoy.das@intel.com> Reviewed-by: Nirmoy Das <nirmoy.das@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240320112730.219854-4-matthew.auld@intel.com
112 lines
2.5 KiB
C
112 lines
2.5 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2022 Intel Corporation
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*/
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#include "xe_bb.h"
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#include "instructions/xe_mi_commands.h"
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#include "regs/xe_gpu_commands.h"
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#include "xe_device.h"
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#include "xe_exec_queue_types.h"
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#include "xe_gt.h"
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#include "xe_hw_fence.h"
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#include "xe_sa.h"
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#include "xe_sched_job.h"
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#include "xe_vm_types.h"
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static int bb_prefetch(struct xe_gt *gt)
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{
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struct xe_device *xe = gt_to_xe(gt);
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if (GRAPHICS_VERx100(xe) >= 1250 && !xe_gt_is_media_type(gt))
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/*
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* RCS and CCS require 1K, although other engines would be
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* okay with 512.
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*/
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return SZ_1K;
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else
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return SZ_512;
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}
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struct xe_bb *xe_bb_new(struct xe_gt *gt, u32 dwords, bool usm)
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{
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struct xe_tile *tile = gt_to_tile(gt);
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struct xe_bb *bb = kmalloc(sizeof(*bb), GFP_KERNEL);
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int err;
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if (!bb)
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return ERR_PTR(-ENOMEM);
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/*
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* We need to allocate space for the requested number of dwords,
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* one additional MI_BATCH_BUFFER_END dword, and additional buffer
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* space to accomodate the platform-specific hardware prefetch
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* requirements.
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*/
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bb->bo = xe_sa_bo_new(!usm ? tile->mem.kernel_bb_pool : gt->usm.bb_pool,
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4 * (dwords + 1) + bb_prefetch(gt));
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if (IS_ERR(bb->bo)) {
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err = PTR_ERR(bb->bo);
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goto err;
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}
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bb->cs = xe_sa_bo_cpu_addr(bb->bo);
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bb->len = 0;
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return bb;
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err:
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kfree(bb);
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return ERR_PTR(err);
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}
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static struct xe_sched_job *
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__xe_bb_create_job(struct xe_exec_queue *q, struct xe_bb *bb, u64 *addr)
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{
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u32 size = drm_suballoc_size(bb->bo);
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bb->cs[bb->len++] = MI_BATCH_BUFFER_END;
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xe_gt_assert(q->gt, bb->len * 4 + bb_prefetch(q->gt) <= size);
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xe_sa_bo_flush_write(bb->bo);
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return xe_sched_job_create(q, addr);
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}
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struct xe_sched_job *xe_bb_create_migration_job(struct xe_exec_queue *q,
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struct xe_bb *bb,
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u64 batch_base_ofs,
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u32 second_idx)
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{
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u64 addr[2] = {
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batch_base_ofs + drm_suballoc_soffset(bb->bo),
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batch_base_ofs + drm_suballoc_soffset(bb->bo) +
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4 * second_idx,
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};
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xe_gt_assert(q->gt, second_idx <= bb->len);
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xe_gt_assert(q->gt, xe_sched_job_is_migration(q));
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xe_gt_assert(q->gt, q->width == 1);
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return __xe_bb_create_job(q, bb, addr);
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}
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struct xe_sched_job *xe_bb_create_job(struct xe_exec_queue *q,
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struct xe_bb *bb)
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{
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u64 addr = xe_sa_bo_gpu_addr(bb->bo);
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xe_gt_assert(q->gt, !xe_sched_job_is_migration(q));
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xe_gt_assert(q->gt, q->width == 1);
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return __xe_bb_create_job(q, bb, &addr);
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}
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void xe_bb_free(struct xe_bb *bb, struct dma_fence *fence)
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{
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if (!bb)
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return;
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xe_sa_bo_free(bb->bo, fence);
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kfree(bb);
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}
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