876611c2b7
Since memory and address spaces are a tile concept rather than a GT concept, we need to plumb tile-based handling through lots of memory-related code. Note that one remaining shortcoming here that will need to be addressed before media GT support can be re-enabled is that although the address space is shared between a tile's GTs, each GT caches the PTEs independently in their own TLB and thus TLB invalidation should be handled at the GT level. v2: - Fix kunit test build. Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://lore.kernel.org/r/20230601215244.678611-13-matthew.d.roper@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
40 lines
945 B
C
40 lines
945 B
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2022 Intel Corporation
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*/
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#ifndef _XE_SA_H_
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#define _XE_SA_H_
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#include "xe_sa_types.h"
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struct dma_fence;
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struct xe_bo;
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struct xe_tile;
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struct xe_sa_manager *xe_sa_bo_manager_init(struct xe_tile *tile, u32 size, u32 align);
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struct drm_suballoc *xe_sa_bo_new(struct xe_sa_manager *sa_manager,
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u32 size);
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void xe_sa_bo_flush_write(struct drm_suballoc *sa_bo);
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void xe_sa_bo_free(struct drm_suballoc *sa_bo,
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struct dma_fence *fence);
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static inline struct xe_sa_manager *
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to_xe_sa_manager(struct drm_suballoc_manager *mng)
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{
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return container_of(mng, struct xe_sa_manager, base);
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}
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static inline u64 xe_sa_bo_gpu_addr(struct drm_suballoc *sa)
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{
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return to_xe_sa_manager(sa->manager)->gpu_addr +
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drm_suballoc_soffset(sa);
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}
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static inline void *xe_sa_bo_cpu_addr(struct drm_suballoc *sa)
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{
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return to_xe_sa_manager(sa->manager)->cpu_ptr +
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drm_suballoc_soffset(sa);
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}
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#endif
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