0d0534750f
Although the vast majority of workarounds the driver needs to implement are either GT-based or display-based, there are occasionally workarounds that reside outside those parts of the hardware (i.e., in they target registers in the sgunit/soc); we can consider these to be "tile" workarounds since there will be instance of these registers per tile. The registers in question should only lose their values during a function-level reset, so they only need to be applied during probe and resume; the registers will not be affected by GT/engine resets. Tile workarounds are rare (there's only one, 22010954014, that's relevant to Xe at the moment) so it's probably not worth updating the xe_rtp design to handle tile-level workarounds yet, although we may want to consider that in the future if/when more of these show up on future platforms. Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Link: https://lore.kernel.org/r/20230913231411.291933-13-matthew.d.roper@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
32 lines
888 B
C
32 lines
888 B
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2022 Intel Corporation
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*/
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#ifndef _XE_WA_
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#define _XE_WA_
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struct drm_printer;
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struct xe_gt;
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struct xe_hw_engine;
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struct xe_tile;
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int xe_wa_init(struct xe_gt *gt);
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void xe_wa_process_oob(struct xe_gt *gt);
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void xe_wa_process_gt(struct xe_gt *gt);
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void xe_wa_process_engine(struct xe_hw_engine *hwe);
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void xe_wa_process_lrc(struct xe_hw_engine *hwe);
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void xe_wa_apply_tile_workarounds(struct xe_tile *tile);
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void xe_reg_whitelist_process_engine(struct xe_hw_engine *hwe);
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void xe_wa_dump(struct xe_gt *gt, struct drm_printer *p);
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/**
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* XE_WA - Out-of-band workarounds, that don't fit the lifecycle any
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* other more specific type
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* @gt__: gt instance
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* @id__: XE_OOB_<id__>, as generated by build system in generated/xe_wa_oob.h
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*/
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#define XE_WA(gt__, id__) test_bit(XE_WA_OOB_ ## id__, (gt__)->wa_active.oob)
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#endif
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