1b5151bd3a
Program live video input format according to selected media bus format. In the bridge mode of operation, DPSUB is connected to FPGA CRTC which almost certainly supports a single media bus format as its output. Expect this to be delivered via the new bridge atomic state. Program DPSUB registers accordingly. Signed-off-by: Anatoliy Klymenko <anatoliy.klymenko@amd.com> Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240416-dp-live-fmt-v4-6-c7f379b7168e@amd.com
69 lines
2 KiB
C
69 lines
2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* ZynqMP Display Driver
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*
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* Copyright (C) 2017 - 2020 Xilinx, Inc.
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*
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* Authors:
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* - Hyun Woo Kwon <hyun.kwon@xilinx.com>
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* - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
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*/
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#ifndef _ZYNQMP_DISP_H_
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#define _ZYNQMP_DISP_H_
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#include <linux/types.h>
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/*
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* 3840x2160 is advertised as the maximum resolution, but almost any
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* resolutions under a 300Mhz pixel rate would work. Pick 4096x4096.
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*/
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#define ZYNQMP_DISP_MAX_WIDTH 4096
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#define ZYNQMP_DISP_MAX_HEIGHT 4096
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/* The DPDMA is limited to 44 bit addressing. */
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#define ZYNQMP_DISP_MAX_DMA_BIT 44
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struct device;
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struct drm_format_info;
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struct drm_plane_state;
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struct platform_device;
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struct zynqmp_disp;
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struct zynqmp_disp_layer;
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struct zynqmp_dpsub;
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/**
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* enum zynqmp_dpsub_layer_id - Layer identifier
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* @ZYNQMP_DPSUB_LAYER_VID: Video layer
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* @ZYNQMP_DPSUB_LAYER_GFX: Graphics layer
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*/
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enum zynqmp_dpsub_layer_id {
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ZYNQMP_DPSUB_LAYER_VID,
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ZYNQMP_DPSUB_LAYER_GFX,
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};
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void zynqmp_disp_enable(struct zynqmp_disp *disp);
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void zynqmp_disp_disable(struct zynqmp_disp *disp);
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int zynqmp_disp_setup_clock(struct zynqmp_disp *disp,
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unsigned long mode_clock);
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void zynqmp_disp_blend_set_global_alpha(struct zynqmp_disp *disp,
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bool enable, u32 alpha);
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u32 *zynqmp_disp_layer_drm_formats(struct zynqmp_disp_layer *layer,
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unsigned int *num_formats);
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u32 *zynqmp_disp_live_layer_formats(struct zynqmp_disp_layer *layer,
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unsigned int *num_formats);
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void zynqmp_disp_layer_enable(struct zynqmp_disp_layer *layer);
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void zynqmp_disp_layer_disable(struct zynqmp_disp_layer *layer);
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void zynqmp_disp_layer_set_format(struct zynqmp_disp_layer *layer,
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const struct drm_format_info *info);
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void zynqmp_disp_layer_set_live_format(struct zynqmp_disp_layer *layer,
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u32 media_bus_format);
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int zynqmp_disp_layer_update(struct zynqmp_disp_layer *layer,
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struct drm_plane_state *state);
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int zynqmp_disp_probe(struct zynqmp_dpsub *dpsub);
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void zynqmp_disp_remove(struct zynqmp_dpsub *dpsub);
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#endif /* _ZYNQMP_DISP_H_ */
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