73e00953c3
Add configuration of more components in MT8195 MDP3. Signed-off-by: Moudy Ho <moudy.ho@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Sebastian Fricke <sebastian.fricke@collabora.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
31 lines
919 B
C
31 lines
919 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2022 MediaTek Inc.
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* Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
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*/
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#ifndef __MDP_REG_HDR_H__
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#define __MDP_REG_HDR_H__
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#define MDP_HDR_TOP (0x000)
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#define MDP_HDR_RELAY (0x004)
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#define MDP_HDR_SIZE_0 (0x014)
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#define MDP_HDR_SIZE_1 (0x018)
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#define MDP_HDR_SIZE_2 (0x01C)
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#define MDP_HDR_HIST_CTRL_0 (0x020)
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#define MDP_HDR_HIST_CTRL_1 (0x024)
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#define MDP_HDR_HIST_ADDR (0x0DC)
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#define MDP_HDR_TILE_POS (0x118)
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/* MASK */
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#define MDP_HDR_RELAY_MASK (0x01)
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#define MDP_HDR_TOP_MASK (0xFF0FEB6D)
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#define MDP_HDR_SIZE_0_MASK (0x1FFF1FFF)
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#define MDP_HDR_SIZE_1_MASK (0x1FFF1FFF)
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#define MDP_HDR_SIZE_2_MASK (0x1FFF1FFF)
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#define MDP_HDR_HIST_CTRL_0_MASK (0x1FFF1FFF)
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#define MDP_HDR_HIST_CTRL_1_MASK (0x1FFF1FFF)
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#define MDP_HDR_HIST_ADDR_MASK (0xBF3F2F3F)
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#define MDP_HDR_TILE_POS_MASK (0x1FFF1FFF)
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#endif // __MDP_REG_HDR_H__
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