73e00953c3
Add configuration of more components in MT8195 MDP3. Signed-off-by: Moudy Ho <moudy.ho@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Sebastian Fricke <sebastian.fricke@collabora.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
41 lines
2 KiB
C
41 lines
2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2022 MediaTek Inc.
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* Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
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*/
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#ifndef __MDP_REG_RSZ_H__
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#define __MDP_REG_RSZ_H__
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#define PRZ_ENABLE 0x000
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#define PRZ_CONTROL_1 0x004
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#define PRZ_CONTROL_2 0x008
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#define PRZ_INPUT_IMAGE 0x010
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#define PRZ_OUTPUT_IMAGE 0x014
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#define PRZ_HORIZONTAL_COEFF_STEP 0x018
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#define PRZ_VERTICAL_COEFF_STEP 0x01c
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#define PRZ_LUMA_HORIZONTAL_INTEGER_OFFSET 0x020
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#define PRZ_LUMA_HORIZONTAL_SUBPIXEL_OFFSET 0x024
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#define PRZ_LUMA_VERTICAL_INTEGER_OFFSET 0x028
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#define PRZ_LUMA_VERTICAL_SUBPIXEL_OFFSET 0x02c
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#define PRZ_CHROMA_HORIZONTAL_INTEGER_OFFSET 0x030
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#define PRZ_CHROMA_HORIZONTAL_SUBPIXEL_OFFSET 0x034
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#define RSZ_ETC_CONTROL 0x22c
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/* MASK */
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#define PRZ_ENABLE_MASK 0x00010001
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#define PRZ_CONTROL_1_MASK 0xfffffff3
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#define PRZ_CONTROL_2_MASK 0x0ffffaff
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#define PRZ_INPUT_IMAGE_MASK 0xffffffff
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#define PRZ_OUTPUT_IMAGE_MASK 0xffffffff
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#define PRZ_HORIZONTAL_COEFF_STEP_MASK 0x007fffff
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#define PRZ_VERTICAL_COEFF_STEP_MASK 0x007fffff
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#define PRZ_LUMA_HORIZONTAL_INTEGER_OFFSET_MASK 0x0000ffff
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#define PRZ_LUMA_HORIZONTAL_SUBPIXEL_OFFSET_MASK 0x001fffff
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#define PRZ_LUMA_VERTICAL_INTEGER_OFFSET_MASK 0x0000ffff
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#define PRZ_LUMA_VERTICAL_SUBPIXEL_OFFSET_MASK 0x001fffff
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#define PRZ_CHROMA_HORIZONTAL_INTEGER_OFFSET_MASK 0x0000ffff
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#define PRZ_CHROMA_HORIZONTAL_SUBPIXEL_OFFSET_MASK 0x001fffff
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#define RSZ_ETC_CONTROL_MASK 0xff770000
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#endif // __MDP_REG_RSZ_H__
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