87a6123753
Zen-based AMD systems report DRAM ECC errors through Unified Memory Controller (UMC) MCA banks. The value provided in MCA_ADDR is a "normalized" address which represents the UMC's view of its managed memory. The normalized address must be translated to a system physical address for software to take action. MI300 systems, uniquely, do not provide a normalized address in MCA_ADDR for DRAM ECC errors. Rather, the "DRAM" address is reported. This value includes identifiers for the bank, row, column, pseudochannel and stack of the memory location. The DRAM address must be converted to a normalized address in order to be further translated to a system physical address. Add helper functions to do the DRAM to normalized translation for MI300 systems. The method is based on the fixed hardware layout of the on-chip memory. [ bp: Massage commit message, decapitalize some, rename function. ] Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com> Co-developed-by: Muralidhara M K <muralidhara.mk@amd.com> Signed-off-by: Muralidhara M K <muralidhara.mk@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Tested-by: Muralidhara M K <muralidhara.mk@amd.com> Link: https://lore.kernel.org/r/20240131165732.88297-1-yazen.ghannam@amd.com
306 lines
7.2 KiB
C
306 lines
7.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* AMD Address Translation Library
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*
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* internal.h : Helper functions and common defines
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*
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* Copyright (c) 2023, Advanced Micro Devices, Inc.
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* All Rights Reserved.
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*
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* Author: Yazen Ghannam <Yazen.Ghannam@amd.com>
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*/
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#ifndef __AMD_ATL_INTERNAL_H__
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#define __AMD_ATL_INTERNAL_H__
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#include <linux/bitfield.h>
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#include <linux/bitops.h>
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#include <linux/ras.h>
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#include <asm/amd_nb.h>
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#include "reg_fields.h"
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/* Maximum possible number of Coherent Stations within a single Data Fabric. */
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#define MAX_COH_ST_CHANNELS 32
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/* PCI ID for Zen4 Server DF Function 0. */
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#define DF_FUNC0_ID_ZEN4_SERVER 0x14AD1022
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/* PCI IDs for MI300 DF Function 0. */
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#define DF_FUNC0_ID_MI300 0x15281022
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/* Shift needed for adjusting register values to true values. */
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#define DF_DRAM_BASE_LIMIT_LSB 28
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#define MI300_DRAM_LIMIT_LSB 20
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enum df_revisions {
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UNKNOWN,
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DF2,
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DF3,
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DF3p5,
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DF4,
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DF4p5,
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};
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/* These are mapped 1:1 to the hardware values. Special cases are set at > 0x20. */
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enum intlv_modes {
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NONE = 0x00,
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NOHASH_2CHAN = 0x01,
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NOHASH_4CHAN = 0x03,
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NOHASH_8CHAN = 0x05,
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DF3_6CHAN = 0x06,
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NOHASH_16CHAN = 0x07,
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NOHASH_32CHAN = 0x08,
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DF3_COD4_2CHAN_HASH = 0x0C,
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DF3_COD2_4CHAN_HASH = 0x0D,
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DF3_COD1_8CHAN_HASH = 0x0E,
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DF4_NPS4_2CHAN_HASH = 0x10,
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DF4_NPS2_4CHAN_HASH = 0x11,
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DF4_NPS1_8CHAN_HASH = 0x12,
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DF4_NPS4_3CHAN_HASH = 0x13,
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DF4_NPS2_6CHAN_HASH = 0x14,
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DF4_NPS1_12CHAN_HASH = 0x15,
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DF4_NPS2_5CHAN_HASH = 0x16,
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DF4_NPS1_10CHAN_HASH = 0x17,
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MI3_HASH_8CHAN = 0x18,
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MI3_HASH_16CHAN = 0x19,
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MI3_HASH_32CHAN = 0x1A,
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DF2_2CHAN_HASH = 0x21,
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/* DF4.5 modes are all IntLvNumChan + 0x20 */
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DF4p5_NPS1_16CHAN_1K_HASH = 0x2C,
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DF4p5_NPS0_24CHAN_1K_HASH = 0x2E,
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DF4p5_NPS4_2CHAN_1K_HASH = 0x30,
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DF4p5_NPS2_4CHAN_1K_HASH = 0x31,
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DF4p5_NPS1_8CHAN_1K_HASH = 0x32,
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DF4p5_NPS4_3CHAN_1K_HASH = 0x33,
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DF4p5_NPS2_6CHAN_1K_HASH = 0x34,
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DF4p5_NPS1_12CHAN_1K_HASH = 0x35,
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DF4p5_NPS2_5CHAN_1K_HASH = 0x36,
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DF4p5_NPS1_10CHAN_1K_HASH = 0x37,
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DF4p5_NPS4_2CHAN_2K_HASH = 0x40,
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DF4p5_NPS2_4CHAN_2K_HASH = 0x41,
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DF4p5_NPS1_8CHAN_2K_HASH = 0x42,
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DF4p5_NPS1_16CHAN_2K_HASH = 0x43,
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DF4p5_NPS4_3CHAN_2K_HASH = 0x44,
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DF4p5_NPS2_6CHAN_2K_HASH = 0x45,
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DF4p5_NPS1_12CHAN_2K_HASH = 0x46,
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DF4p5_NPS0_24CHAN_2K_HASH = 0x47,
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DF4p5_NPS2_5CHAN_2K_HASH = 0x48,
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DF4p5_NPS1_10CHAN_2K_HASH = 0x49,
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};
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struct df_flags {
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__u8 legacy_ficaa : 1,
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socket_id_shift_quirk : 1,
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heterogeneous : 1,
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__reserved_0 : 5;
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};
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struct df_config {
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enum df_revisions rev;
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/*
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* These masks operate on the 16-bit Coherent Station IDs,
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* e.g. Instance, Fabric, Destination, etc.
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*/
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u16 component_id_mask;
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u16 die_id_mask;
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u16 node_id_mask;
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u16 socket_id_mask;
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/*
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* Least-significant bit of Node ID portion of the
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* system-wide Coherent Station Fabric ID.
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*/
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u8 node_id_shift;
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/*
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* Least-significant bit of Die portion of the Node ID.
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* Adjusted to include the Node ID shift in order to apply
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* to the Coherent Station Fabric ID.
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*/
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u8 die_id_shift;
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/*
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* Least-significant bit of Socket portion of the Node ID.
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* Adjusted to include the Node ID shift in order to apply
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* to the Coherent Station Fabric ID.
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*/
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u8 socket_id_shift;
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/* Number of DRAM Address maps visible in a Coherent Station. */
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u8 num_coh_st_maps;
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/* Global flags to handle special cases. */
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struct df_flags flags;
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};
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extern struct df_config df_cfg;
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struct dram_addr_map {
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/*
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* Each DRAM Address Map can operate independently
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* in different interleaving modes.
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*/
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enum intlv_modes intlv_mode;
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/* System-wide number for this address map. */
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u8 num;
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/* Raw register values */
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u32 base;
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u32 limit;
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u32 ctl;
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u32 intlv;
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/*
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* Logical to Physical Coherent Station Remapping array
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*
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* Index: Logical Coherent Station Instance ID
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* Value: Physical Coherent Station Instance ID
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*
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* phys_coh_st_inst_id = remap_array[log_coh_st_inst_id]
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*/
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u8 remap_array[MAX_COH_ST_CHANNELS];
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/*
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* Number of bits covering DRAM Address map 0
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* when interleaving is non-power-of-2.
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*
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* Used only for DF3_6CHAN.
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*/
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u8 np2_bits;
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/* Position of the 'interleave bit'. */
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u8 intlv_bit_pos;
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/* Number of channels interleaved in this map. */
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u8 num_intlv_chan;
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/* Number of dies interleaved in this map. */
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u8 num_intlv_dies;
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/* Number of sockets interleaved in this map. */
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u8 num_intlv_sockets;
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/*
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* Total number of channels interleaved accounting
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* for die and socket interleaving.
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*/
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u8 total_intlv_chan;
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/* Total bits needed to cover 'total_intlv_chan'. */
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u8 total_intlv_bits;
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};
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/* Original input values cached for debug printing. */
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struct addr_ctx_inputs {
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u64 norm_addr;
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u8 socket_id;
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u8 die_id;
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u8 coh_st_inst_id;
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};
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struct addr_ctx {
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u64 ret_addr;
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struct addr_ctx_inputs inputs;
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struct dram_addr_map map;
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/* AMD Node ID calculated from Socket and Die IDs. */
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u8 node_id;
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/*
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* Coherent Station Instance ID
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* Local ID used within a 'node'.
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*/
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u16 inst_id;
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/*
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* Coherent Station Fabric ID
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* System-wide ID that includes 'node' bits.
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*/
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u16 coh_st_fabric_id;
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};
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int df_indirect_read_instance(u16 node, u8 func, u16 reg, u8 instance_id, u32 *lo);
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int df_indirect_read_broadcast(u16 node, u8 func, u16 reg, u32 *lo);
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int get_df_system_info(void);
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int determine_node_id(struct addr_ctx *ctx, u8 socket_num, u8 die_num);
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int get_addr_hash_mi300(void);
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int get_address_map(struct addr_ctx *ctx);
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int denormalize_address(struct addr_ctx *ctx);
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int dehash_address(struct addr_ctx *ctx);
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unsigned long norm_to_sys_addr(u8 socket_id, u8 die_id, u8 coh_st_inst_id, unsigned long addr);
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unsigned long convert_umc_mca_addr_to_sys_addr(struct atl_err *err);
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/*
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* Make a gap in @data that is @num_bits long starting at @bit_num.
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* e.g. data = 11111111'b
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* bit_num = 3
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* num_bits = 2
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* result = 1111100111'b
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*/
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static inline u64 expand_bits(u8 bit_num, u8 num_bits, u64 data)
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{
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u64 temp1, temp2;
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if (!num_bits)
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return data;
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if (!bit_num) {
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WARN_ON_ONCE(num_bits >= BITS_PER_LONG);
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return data << num_bits;
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}
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WARN_ON_ONCE(bit_num >= BITS_PER_LONG);
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temp1 = data & GENMASK_ULL(bit_num - 1, 0);
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temp2 = data & GENMASK_ULL(63, bit_num);
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temp2 <<= num_bits;
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return temp1 | temp2;
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}
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/*
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* Remove bits in @data between @low_bit and @high_bit inclusive.
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* e.g. data = XXXYYZZZ'b
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* low_bit = 3
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* high_bit = 4
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* result = XXXZZZ'b
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*/
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static inline u64 remove_bits(u8 low_bit, u8 high_bit, u64 data)
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{
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u64 temp1, temp2;
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WARN_ON_ONCE(high_bit >= BITS_PER_LONG);
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WARN_ON_ONCE(low_bit >= BITS_PER_LONG);
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WARN_ON_ONCE(low_bit > high_bit);
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if (!low_bit)
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return data >> (high_bit++);
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temp1 = GENMASK_ULL(low_bit - 1, 0) & data;
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temp2 = GENMASK_ULL(63, high_bit + 1) & data;
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temp2 >>= high_bit - low_bit + 1;
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return temp1 | temp2;
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}
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#define atl_debug(ctx, fmt, arg...) \
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pr_debug("socket_id=%u die_id=%u coh_st_inst_id=%u norm_addr=0x%016llx: " fmt,\
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(ctx)->inputs.socket_id, (ctx)->inputs.die_id,\
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(ctx)->inputs.coh_st_inst_id, (ctx)->inputs.norm_addr, ##arg)
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static inline void atl_debug_on_bad_df_rev(void)
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{
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pr_debug("Unrecognized DF rev: %u", df_cfg.rev);
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}
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static inline void atl_debug_on_bad_intlv_mode(struct addr_ctx *ctx)
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{
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atl_debug(ctx, "Unrecognized interleave mode: %u", ctx->map.intlv_mode);
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}
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#endif /* __AMD_ATL_INTERNAL_H__ */
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