8f76c0f4c3
Currently big amount of the functions returning standard error codes are of type s32. Convert them to regular ints as typdefs here are not necessary to return standard error codes. Fix incorrect args alignment in touched functions. Suggested-by: Jacob Keller <jacob.e.keller@intel.com> Reviewed-by: Jacob Keller <jacob.e.keller@intel.com> Reviewed-by: Simon Horman <horms@kernel.org> Signed-off-by: Jedrzej Jagielski <jedrzej.jagielski@intel.com> Tested-by: Pucha Himasekhar Reddy <himasekharx.reddy.pucha@intel.com> (A Contingent worker at Intel) Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
347 lines
9.4 KiB
C
347 lines
9.4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/* Copyright(c) 1999 - 2018 Intel Corporation. */
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#include "ixgbe.h"
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#include "ixgbe_type.h"
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#include "ixgbe_dcb.h"
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#include "ixgbe_dcb_82599.h"
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/**
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* ixgbe_dcb_config_rx_arbiter_82599 - Config Rx Data arbiter
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* @hw: pointer to hardware structure
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* @refill: refill credits index by traffic class
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* @max: max credits index by traffic class
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* @bwg_id: bandwidth grouping indexed by traffic class
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* @prio_type: priority type indexed by traffic class
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* @prio_tc: priority to tc assignments indexed by priority
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*
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* Configure Rx Packet Arbiter and credits for each traffic class.
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*/
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int ixgbe_dcb_config_rx_arbiter_82599(struct ixgbe_hw *hw,
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u16 *refill,
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u16 *max,
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u8 *bwg_id,
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u8 *prio_type,
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u8 *prio_tc)
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{
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u32 reg = 0;
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u32 credit_refill = 0;
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u32 credit_max = 0;
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u8 i = 0;
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/*
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* Disable the arbiter before changing parameters
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* (always enable recycle mode; WSP)
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*/
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reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS;
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IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
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/* Map all traffic classes to their UP */
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reg = 0;
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for (i = 0; i < MAX_USER_PRIORITY; i++)
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reg |= (prio_tc[i] << (i * IXGBE_RTRUP2TC_UP_SHIFT));
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IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
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/* Configure traffic class credits and priority */
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for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
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credit_refill = refill[i];
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credit_max = max[i];
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reg = credit_refill | (credit_max << IXGBE_RTRPT4C_MCL_SHIFT);
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reg |= (u32)(bwg_id[i]) << IXGBE_RTRPT4C_BWG_SHIFT;
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if (prio_type[i] == prio_link)
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reg |= IXGBE_RTRPT4C_LSP;
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IXGBE_WRITE_REG(hw, IXGBE_RTRPT4C(i), reg);
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}
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/*
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* Configure Rx packet plane (recycle mode; WSP) and
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* enable arbiter
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*/
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reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC;
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IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
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return 0;
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}
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/**
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* ixgbe_dcb_config_tx_desc_arbiter_82599 - Config Tx Desc. arbiter
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* @hw: pointer to hardware structure
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* @refill: refill credits index by traffic class
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* @max: max credits index by traffic class
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* @bwg_id: bandwidth grouping indexed by traffic class
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* @prio_type: priority type indexed by traffic class
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*
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* Configure Tx Descriptor Arbiter and credits for each traffic class.
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*/
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int ixgbe_dcb_config_tx_desc_arbiter_82599(struct ixgbe_hw *hw,
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u16 *refill,
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u16 *max,
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u8 *bwg_id,
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u8 *prio_type)
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{
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u32 reg, max_credits;
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u8 i;
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/* Clear the per-Tx queue credits; we use per-TC instead */
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for (i = 0; i < 128; i++) {
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IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
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IXGBE_WRITE_REG(hw, IXGBE_RTTDT1C, 0);
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}
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/* Configure traffic class credits and priority */
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for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
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max_credits = max[i];
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reg = max_credits << IXGBE_RTTDT2C_MCL_SHIFT;
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reg |= refill[i];
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reg |= (u32)(bwg_id[i]) << IXGBE_RTTDT2C_BWG_SHIFT;
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if (prio_type[i] == prio_group)
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reg |= IXGBE_RTTDT2C_GSP;
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if (prio_type[i] == prio_link)
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reg |= IXGBE_RTTDT2C_LSP;
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IXGBE_WRITE_REG(hw, IXGBE_RTTDT2C(i), reg);
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}
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/*
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* Configure Tx descriptor plane (recycle mode; WSP) and
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* enable arbiter
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*/
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reg = IXGBE_RTTDCS_TDPAC | IXGBE_RTTDCS_TDRM;
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IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
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return 0;
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}
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/**
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* ixgbe_dcb_config_tx_data_arbiter_82599 - Config Tx Data arbiter
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* @hw: pointer to hardware structure
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* @refill: refill credits index by traffic class
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* @max: max credits index by traffic class
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* @bwg_id: bandwidth grouping indexed by traffic class
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* @prio_type: priority type indexed by traffic class
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* @prio_tc: priority to tc assignments indexed by priority
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*
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* Configure Tx Packet Arbiter and credits for each traffic class.
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*/
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int ixgbe_dcb_config_tx_data_arbiter_82599(struct ixgbe_hw *hw,
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u16 *refill,
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u16 *max,
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u8 *bwg_id,
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u8 *prio_type,
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u8 *prio_tc)
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{
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u32 reg;
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u8 i;
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/*
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* Disable the arbiter before changing parameters
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* (always enable recycle mode; SP; arb delay)
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*/
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reg = IXGBE_RTTPCS_TPPAC | IXGBE_RTTPCS_TPRM |
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(IXGBE_RTTPCS_ARBD_DCB << IXGBE_RTTPCS_ARBD_SHIFT) |
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IXGBE_RTTPCS_ARBDIS;
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IXGBE_WRITE_REG(hw, IXGBE_RTTPCS, reg);
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/* Map all traffic classes to their UP */
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reg = 0;
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for (i = 0; i < MAX_USER_PRIORITY; i++)
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reg |= (prio_tc[i] << (i * IXGBE_RTTUP2TC_UP_SHIFT));
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IXGBE_WRITE_REG(hw, IXGBE_RTTUP2TC, reg);
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/* Configure traffic class credits and priority */
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for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
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reg = refill[i];
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reg |= (u32)(max[i]) << IXGBE_RTTPT2C_MCL_SHIFT;
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reg |= (u32)(bwg_id[i]) << IXGBE_RTTPT2C_BWG_SHIFT;
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if (prio_type[i] == prio_group)
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reg |= IXGBE_RTTPT2C_GSP;
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if (prio_type[i] == prio_link)
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reg |= IXGBE_RTTPT2C_LSP;
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IXGBE_WRITE_REG(hw, IXGBE_RTTPT2C(i), reg);
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}
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/*
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* Configure Tx packet plane (recycle mode; SP; arb delay) and
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* enable arbiter
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*/
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reg = IXGBE_RTTPCS_TPPAC | IXGBE_RTTPCS_TPRM |
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(IXGBE_RTTPCS_ARBD_DCB << IXGBE_RTTPCS_ARBD_SHIFT);
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IXGBE_WRITE_REG(hw, IXGBE_RTTPCS, reg);
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return 0;
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}
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/**
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* ixgbe_dcb_config_pfc_82599 - Configure priority flow control
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* @hw: pointer to hardware structure
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* @pfc_en: enabled pfc bitmask
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* @prio_tc: priority to tc assignments indexed by priority
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*
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* Configure Priority Flow Control (PFC) for each traffic class.
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*/
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int ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw, u8 pfc_en, u8 *prio_tc)
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{
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u32 i, j, fcrtl, reg;
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u8 max_tc = 0;
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/* Enable Transmit Priority Flow Control */
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IXGBE_WRITE_REG(hw, IXGBE_FCCFG, IXGBE_FCCFG_TFCE_PRIORITY);
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/* Enable Receive Priority Flow Control */
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reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
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reg |= IXGBE_MFLCN_DPF;
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/*
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* X540 & X550 supports per TC Rx priority flow control.
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* So clear all TCs and only enable those that should be
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* enabled.
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*/
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reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);
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if (hw->mac.type >= ixgbe_mac_X540)
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reg |= pfc_en << IXGBE_MFLCN_RPFCE_SHIFT;
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if (pfc_en)
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reg |= IXGBE_MFLCN_RPFCE;
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IXGBE_WRITE_REG(hw, IXGBE_MFLCN, reg);
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for (i = 0; i < MAX_USER_PRIORITY; i++) {
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if (prio_tc[i] > max_tc)
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max_tc = prio_tc[i];
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}
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/* Configure PFC Tx thresholds per TC */
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for (i = 0; i <= max_tc; i++) {
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int enabled = 0;
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for (j = 0; j < MAX_USER_PRIORITY; j++) {
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if ((prio_tc[j] == i) && (pfc_en & BIT(j))) {
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enabled = 1;
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break;
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}
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}
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if (enabled) {
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reg = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
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fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
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IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
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} else {
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/* In order to prevent Tx hangs when the internal Tx
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* switch is enabled we must set the high water mark
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* to the Rx packet buffer size - 24KB. This allows
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* the Tx switch to function even under heavy Rx
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* workloads.
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*/
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reg = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576;
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IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
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}
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IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), reg);
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}
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for (; i < MAX_TRAFFIC_CLASS; i++) {
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IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
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IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), 0);
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}
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/* Configure pause time (2 TCs per register) */
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reg = hw->fc.pause_time * 0x00010001;
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for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++)
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IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
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/* Configure flow control refresh threshold value */
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IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
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return 0;
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}
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/**
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* ixgbe_dcb_config_tc_stats_82599 - Config traffic class statistics
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* @hw: pointer to hardware structure
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*
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* Configure queue statistics registers, all queues belonging to same traffic
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* class uses a single set of queue statistics counters.
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*/
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static int ixgbe_dcb_config_tc_stats_82599(struct ixgbe_hw *hw)
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{
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u32 reg = 0;
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u8 i = 0;
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/*
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* Receive Queues stats setting
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* 32 RQSMR registers, each configuring 4 queues.
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* Set all 16 queues of each TC to the same stat
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* with TC 'n' going to stat 'n'.
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*/
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for (i = 0; i < 32; i++) {
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reg = 0x01010101 * (i / 4);
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IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg);
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}
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/*
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* Transmit Queues stats setting
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* 32 TQSM registers, each controlling 4 queues.
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* Set all queues of each TC to the same stat
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* with TC 'n' going to stat 'n'.
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* Tx queues are allocated non-uniformly to TCs:
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* 32, 32, 16, 16, 8, 8, 8, 8.
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*/
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for (i = 0; i < 32; i++) {
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if (i < 8)
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reg = 0x00000000;
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else if (i < 16)
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reg = 0x01010101;
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else if (i < 20)
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reg = 0x02020202;
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else if (i < 24)
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reg = 0x03030303;
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else if (i < 26)
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reg = 0x04040404;
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else if (i < 28)
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reg = 0x05050505;
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else if (i < 30)
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reg = 0x06060606;
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else
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reg = 0x07070707;
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IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), reg);
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}
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return 0;
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}
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/**
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* ixgbe_dcb_hw_config_82599 - Configure and enable DCB
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* @hw: pointer to hardware structure
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* @pfc_en: enabled pfc bitmask
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* @refill: refill credits index by traffic class
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* @max: max credits index by traffic class
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* @bwg_id: bandwidth grouping indexed by traffic class
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* @prio_type: priority type indexed by traffic class
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* @prio_tc: priority to tc assignments indexed by priority
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*
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* Configure dcb settings and enable dcb mode.
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*/
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int ixgbe_dcb_hw_config_82599(struct ixgbe_hw *hw, u8 pfc_en, u16 *refill,
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u16 *max, u8 *bwg_id, u8 *prio_type, u8 *prio_tc)
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{
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ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id,
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prio_type, prio_tc);
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ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max,
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bwg_id, prio_type);
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ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max,
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bwg_id, prio_type, prio_tc);
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ixgbe_dcb_config_pfc_82599(hw, pfc_en, prio_tc);
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ixgbe_dcb_config_tc_stats_82599(hw);
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return 0;
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}
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