6606515742
The "force" argument to write_spec_ctrl_current() is currently ambiguous
as it does not guarantee the MSR write. This is due to the optimization
that writes to the MSR happen only when the new value differs from the
cached value.
This is fine in most cases, but breaks for S3 resume when the cached MSR
value gets out of sync with the hardware MSR value due to S3 resetting
it.
When x86_spec_ctrl_current is same as x86_spec_ctrl_base, the MSR write
is skipped. Which results in SPEC_CTRL mitigations not getting restored.
Move the MSR write from write_spec_ctrl_current() to a new function that
unconditionally writes to the MSR. Update the callers accordingly and
rename functions.
[ bp: Rework a bit. ]
Fixes: caa0ff24d5 ("x86/bugs: Keep a per-CPU IA32_SPEC_CTRL value")
Suggested-by: Borislav Petkov <bp@alien8.de>
Signed-off-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Cc: <stable@kernel.org>
Link: https://lore.kernel.org/r/806d39b0bfec2fe8f50dc5446dff20f5bb24a959.1669821572.git.pawan.kumar.gupta@linux.intel.com
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
411 lines
11 KiB
C
411 lines
11 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_X86_NOSPEC_BRANCH_H_
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#define _ASM_X86_NOSPEC_BRANCH_H_
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#include <linux/static_key.h>
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#include <linux/objtool.h>
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#include <linux/linkage.h>
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#include <asm/alternative.h>
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#include <asm/cpufeatures.h>
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#include <asm/msr-index.h>
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#include <asm/unwind_hints.h>
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#include <asm/percpu.h>
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#define RETPOLINE_THUNK_SIZE 32
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/*
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* Fill the CPU return stack buffer.
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*
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* Each entry in the RSB, if used for a speculative 'ret', contains an
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* infinite 'pause; lfence; jmp' loop to capture speculative execution.
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*
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* This is required in various cases for retpoline and IBRS-based
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* mitigations for the Spectre variant 2 vulnerability. Sometimes to
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* eliminate potentially bogus entries from the RSB, and sometimes
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* purely to ensure that it doesn't get empty, which on some CPUs would
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* allow predictions from other (unwanted!) sources to be used.
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*
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* We define a CPP macro such that it can be used from both .S files and
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* inline assembly. It's possible to do a .macro and then include that
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* from C via asm(".include <asm/nospec-branch.h>") but let's not go there.
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*/
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#define RSB_CLEAR_LOOPS 32 /* To forcibly overwrite all entries */
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/*
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* Common helper for __FILL_RETURN_BUFFER and __FILL_ONE_RETURN.
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*/
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#define __FILL_RETURN_SLOT \
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ANNOTATE_INTRA_FUNCTION_CALL; \
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call 772f; \
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int3; \
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772:
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/*
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* Stuff the entire RSB.
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*
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* Google experimented with loop-unrolling and this turned out to be
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* the optimal version - two calls, each with their own speculation
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* trap should their return address end up getting used, in a loop.
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*/
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#ifdef CONFIG_X86_64
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#define __FILL_RETURN_BUFFER(reg, nr) \
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mov $(nr/2), reg; \
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771: \
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__FILL_RETURN_SLOT \
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__FILL_RETURN_SLOT \
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add $(BITS_PER_LONG/8) * 2, %_ASM_SP; \
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dec reg; \
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jnz 771b; \
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/* barrier for jnz misprediction */ \
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lfence;
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#else
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/*
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* i386 doesn't unconditionally have LFENCE, as such it can't
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* do a loop.
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*/
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#define __FILL_RETURN_BUFFER(reg, nr) \
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.rept nr; \
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__FILL_RETURN_SLOT; \
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.endr; \
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add $(BITS_PER_LONG/8) * nr, %_ASM_SP;
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#endif
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/*
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* Stuff a single RSB slot.
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*
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* To mitigate Post-Barrier RSB speculation, one CALL instruction must be
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* forced to retire before letting a RET instruction execute.
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*
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* On PBRSB-vulnerable CPUs, it is not safe for a RET to be executed
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* before this point.
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*/
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#define __FILL_ONE_RETURN \
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__FILL_RETURN_SLOT \
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add $(BITS_PER_LONG/8), %_ASM_SP; \
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lfence;
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#ifdef __ASSEMBLY__
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/*
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* This should be used immediately before an indirect jump/call. It tells
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* objtool the subsequent indirect jump/call is vouched safe for retpoline
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* builds.
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*/
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.macro ANNOTATE_RETPOLINE_SAFE
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.Lannotate_\@:
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.pushsection .discard.retpoline_safe
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_ASM_PTR .Lannotate_\@
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.popsection
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.endm
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/*
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* (ab)use RETPOLINE_SAFE on RET to annotate away 'bare' RET instructions
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* vs RETBleed validation.
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*/
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#define ANNOTATE_UNRET_SAFE ANNOTATE_RETPOLINE_SAFE
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/*
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* Abuse ANNOTATE_RETPOLINE_SAFE on a NOP to indicate UNRET_END, should
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* eventually turn into it's own annotation.
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*/
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.macro ANNOTATE_UNRET_END
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#ifdef CONFIG_DEBUG_ENTRY
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ANNOTATE_RETPOLINE_SAFE
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nop
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#endif
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.endm
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/*
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* Equivalent to -mindirect-branch-cs-prefix; emit the 5 byte jmp/call
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* to the retpoline thunk with a CS prefix when the register requires
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* a RAX prefix byte to encode. Also see apply_retpolines().
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*/
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.macro __CS_PREFIX reg:req
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.irp rs,r8,r9,r10,r11,r12,r13,r14,r15
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.ifc \reg,\rs
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.byte 0x2e
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.endif
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.endr
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.endm
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/*
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* JMP_NOSPEC and CALL_NOSPEC macros can be used instead of a simple
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* indirect jmp/call which may be susceptible to the Spectre variant 2
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* attack.
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*/
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.macro JMP_NOSPEC reg:req
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#ifdef CONFIG_RETPOLINE
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__CS_PREFIX \reg
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jmp __x86_indirect_thunk_\reg
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#else
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jmp *%\reg
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int3
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#endif
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.endm
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.macro CALL_NOSPEC reg:req
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#ifdef CONFIG_RETPOLINE
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__CS_PREFIX \reg
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call __x86_indirect_thunk_\reg
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#else
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call *%\reg
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#endif
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.endm
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/*
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* A simpler FILL_RETURN_BUFFER macro. Don't make people use the CPP
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* monstrosity above, manually.
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*/
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.macro FILL_RETURN_BUFFER reg:req nr:req ftr:req ftr2=ALT_NOT(X86_FEATURE_ALWAYS)
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ALTERNATIVE_2 "jmp .Lskip_rsb_\@", \
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__stringify(__FILL_RETURN_BUFFER(\reg,\nr)), \ftr, \
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__stringify(__FILL_ONE_RETURN), \ftr2
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.Lskip_rsb_\@:
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.endm
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#ifdef CONFIG_CPU_UNRET_ENTRY
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#define CALL_ZEN_UNTRAIN_RET "call zen_untrain_ret"
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#else
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#define CALL_ZEN_UNTRAIN_RET ""
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#endif
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/*
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* Mitigate RETBleed for AMD/Hygon Zen uarch. Requires KERNEL CR3 because the
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* return thunk isn't mapped into the userspace tables (then again, AMD
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* typically has NO_MELTDOWN).
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*
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* While zen_untrain_ret() doesn't clobber anything but requires stack,
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* entry_ibpb() will clobber AX, CX, DX.
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*
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* As such, this must be placed after every *SWITCH_TO_KERNEL_CR3 at a point
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* where we have a stack but before any RET instruction.
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*/
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.macro UNTRAIN_RET
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#if defined(CONFIG_CPU_UNRET_ENTRY) || defined(CONFIG_CPU_IBPB_ENTRY)
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ANNOTATE_UNRET_END
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ALTERNATIVE_2 "", \
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CALL_ZEN_UNTRAIN_RET, X86_FEATURE_UNRET, \
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"call entry_ibpb", X86_FEATURE_ENTRY_IBPB
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#endif
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.endm
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#else /* __ASSEMBLY__ */
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#define ANNOTATE_RETPOLINE_SAFE \
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"999:\n\t" \
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".pushsection .discard.retpoline_safe\n\t" \
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_ASM_PTR " 999b\n\t" \
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".popsection\n\t"
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typedef u8 retpoline_thunk_t[RETPOLINE_THUNK_SIZE];
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extern retpoline_thunk_t __x86_indirect_thunk_array[];
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extern void __x86_return_thunk(void);
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extern void zen_untrain_ret(void);
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extern void entry_ibpb(void);
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#ifdef CONFIG_RETPOLINE
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#define GEN(reg) \
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extern retpoline_thunk_t __x86_indirect_thunk_ ## reg;
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#include <asm/GEN-for-each-reg.h>
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#undef GEN
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#ifdef CONFIG_X86_64
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/*
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* Inline asm uses the %V modifier which is only in newer GCC
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* which is ensured when CONFIG_RETPOLINE is defined.
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*/
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# define CALL_NOSPEC \
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ALTERNATIVE_2( \
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ANNOTATE_RETPOLINE_SAFE \
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"call *%[thunk_target]\n", \
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"call __x86_indirect_thunk_%V[thunk_target]\n", \
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X86_FEATURE_RETPOLINE, \
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"lfence;\n" \
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ANNOTATE_RETPOLINE_SAFE \
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"call *%[thunk_target]\n", \
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X86_FEATURE_RETPOLINE_LFENCE)
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# define THUNK_TARGET(addr) [thunk_target] "r" (addr)
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#else /* CONFIG_X86_32 */
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/*
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* For i386 we use the original ret-equivalent retpoline, because
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* otherwise we'll run out of registers. We don't care about CET
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* here, anyway.
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*/
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# define CALL_NOSPEC \
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ALTERNATIVE_2( \
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ANNOTATE_RETPOLINE_SAFE \
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"call *%[thunk_target]\n", \
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" jmp 904f;\n" \
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" .align 16\n" \
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"901: call 903f;\n" \
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"902: pause;\n" \
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" lfence;\n" \
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" jmp 902b;\n" \
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" .align 16\n" \
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"903: lea 4(%%esp), %%esp;\n" \
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" pushl %[thunk_target];\n" \
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" ret;\n" \
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" .align 16\n" \
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"904: call 901b;\n", \
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X86_FEATURE_RETPOLINE, \
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"lfence;\n" \
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ANNOTATE_RETPOLINE_SAFE \
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"call *%[thunk_target]\n", \
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X86_FEATURE_RETPOLINE_LFENCE)
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# define THUNK_TARGET(addr) [thunk_target] "rm" (addr)
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#endif
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#else /* No retpoline for C / inline asm */
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# define CALL_NOSPEC "call *%[thunk_target]\n"
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# define THUNK_TARGET(addr) [thunk_target] "rm" (addr)
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#endif
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/* The Spectre V2 mitigation variants */
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enum spectre_v2_mitigation {
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SPECTRE_V2_NONE,
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SPECTRE_V2_RETPOLINE,
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SPECTRE_V2_LFENCE,
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SPECTRE_V2_EIBRS,
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SPECTRE_V2_EIBRS_RETPOLINE,
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SPECTRE_V2_EIBRS_LFENCE,
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SPECTRE_V2_IBRS,
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};
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/* The indirect branch speculation control variants */
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enum spectre_v2_user_mitigation {
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SPECTRE_V2_USER_NONE,
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SPECTRE_V2_USER_STRICT,
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SPECTRE_V2_USER_STRICT_PREFERRED,
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SPECTRE_V2_USER_PRCTL,
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SPECTRE_V2_USER_SECCOMP,
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};
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/* The Speculative Store Bypass disable variants */
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enum ssb_mitigation {
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SPEC_STORE_BYPASS_NONE,
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SPEC_STORE_BYPASS_DISABLE,
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SPEC_STORE_BYPASS_PRCTL,
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SPEC_STORE_BYPASS_SECCOMP,
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};
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extern char __indirect_thunk_start[];
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extern char __indirect_thunk_end[];
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static __always_inline
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void alternative_msr_write(unsigned int msr, u64 val, unsigned int feature)
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{
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asm volatile(ALTERNATIVE("", "wrmsr", %c[feature])
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: : "c" (msr),
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"a" ((u32)val),
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"d" ((u32)(val >> 32)),
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[feature] "i" (feature)
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: "memory");
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}
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static inline void indirect_branch_prediction_barrier(void)
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{
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u64 val = PRED_CMD_IBPB;
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alternative_msr_write(MSR_IA32_PRED_CMD, val, X86_FEATURE_USE_IBPB);
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}
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/* The Intel SPEC CTRL MSR base value cache */
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extern u64 x86_spec_ctrl_base;
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DECLARE_PER_CPU(u64, x86_spec_ctrl_current);
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extern void update_spec_ctrl_cond(u64 val);
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extern u64 spec_ctrl_current(void);
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/*
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* With retpoline, we must use IBRS to restrict branch prediction
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* before calling into firmware.
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*
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* (Implemented as CPP macros due to header hell.)
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*/
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#define firmware_restrict_branch_speculation_start() \
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do { \
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preempt_disable(); \
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alternative_msr_write(MSR_IA32_SPEC_CTRL, \
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spec_ctrl_current() | SPEC_CTRL_IBRS, \
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X86_FEATURE_USE_IBRS_FW); \
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alternative_msr_write(MSR_IA32_PRED_CMD, PRED_CMD_IBPB, \
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X86_FEATURE_USE_IBPB_FW); \
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} while (0)
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#define firmware_restrict_branch_speculation_end() \
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do { \
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alternative_msr_write(MSR_IA32_SPEC_CTRL, \
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spec_ctrl_current(), \
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X86_FEATURE_USE_IBRS_FW); \
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preempt_enable(); \
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} while (0)
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DECLARE_STATIC_KEY_FALSE(switch_to_cond_stibp);
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DECLARE_STATIC_KEY_FALSE(switch_mm_cond_ibpb);
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DECLARE_STATIC_KEY_FALSE(switch_mm_always_ibpb);
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DECLARE_STATIC_KEY_FALSE(mds_user_clear);
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DECLARE_STATIC_KEY_FALSE(mds_idle_clear);
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DECLARE_STATIC_KEY_FALSE(switch_mm_cond_l1d_flush);
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DECLARE_STATIC_KEY_FALSE(mmio_stale_data_clear);
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#include <asm/segment.h>
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/**
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* mds_clear_cpu_buffers - Mitigation for MDS and TAA vulnerability
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*
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* This uses the otherwise unused and obsolete VERW instruction in
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* combination with microcode which triggers a CPU buffer flush when the
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* instruction is executed.
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*/
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static __always_inline void mds_clear_cpu_buffers(void)
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{
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static const u16 ds = __KERNEL_DS;
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/*
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* Has to be the memory-operand variant because only that
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* guarantees the CPU buffer flush functionality according to
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* documentation. The register-operand variant does not.
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* Works with any segment selector, but a valid writable
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* data segment is the fastest variant.
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*
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* "cc" clobber is required because VERW modifies ZF.
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*/
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asm volatile("verw %[ds]" : : [ds] "m" (ds) : "cc");
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}
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/**
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* mds_user_clear_cpu_buffers - Mitigation for MDS and TAA vulnerability
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*
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* Clear CPU buffers if the corresponding static key is enabled
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*/
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static __always_inline void mds_user_clear_cpu_buffers(void)
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{
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if (static_branch_likely(&mds_user_clear))
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mds_clear_cpu_buffers();
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}
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/**
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* mds_idle_clear_cpu_buffers - Mitigation for MDS vulnerability
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*
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* Clear CPU buffers if the corresponding static key is enabled
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*/
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static inline void mds_idle_clear_cpu_buffers(void)
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{
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if (static_branch_likely(&mds_idle_clear))
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mds_clear_cpu_buffers();
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}
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_X86_NOSPEC_BRANCH_H_ */
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