54c2cc7919
Here is the "big" set of USB and Thunderbolt driver changes for
5.18-rc1. For the most part it's been a quiet development cycle for the
USB core, but there are the usual "hot spots" of development activity.
Included in here are:
- Thunderbolt driver updates:
- fixes for devices without displayport adapters
- lane bonding support and improvements
- other minor changes based on device testing
- dwc3 gadget driver changes. It seems this driver will never
be finished given that the IP core is showing up in zillions
of new devices and each implementation decides to do something
different with it...
- uvc gadget driver updates as more devices start to use and
rely on this hardware as well
- usb_maxpacket() api changes to remove an unneeded and unused
parameter.
- usb-serial driver device id updates and small cleanups
- typec cleanups and fixes based on device testing
- device tree updates for usb properties
- lots of other small fixes and driver updates.
All of these have been in linux-next for weeks with no reported
problems.
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Merge tag 'usb-5.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb
Pull USB / Thunderbolt updates from Greg KH:
"Here is the "big" set of USB and Thunderbolt driver changes for
5.18-rc1. For the most part it's been a quiet development cycle for
the USB core, but there are the usual "hot spots" of development
activity.
Included in here are:
- Thunderbolt driver updates:
- fixes for devices without displayport adapters
- lane bonding support and improvements
- other minor changes based on device testing
- dwc3 gadget driver changes.
It seems this driver will never be finished given that the IP core
is showing up in zillions of new devices and each implementation
decides to do something different with it...
- uvc gadget driver updates as more devices start to use and rely on
this hardware as well
- usb_maxpacket() api changes to remove an unneeded and unused
parameter.
- usb-serial driver device id updates and small cleanups
- typec cleanups and fixes based on device testing
- device tree updates for usb properties
- lots of other small fixes and driver updates.
All of these have been in linux-next for weeks with no reported
problems"
* tag 'usb-5.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb: (154 commits)
USB: new quirk for Dell Gen 2 devices
usb: dwc3: core: Add error log when core soft reset failed
usb: dwc3: gadget: Move null pinter check to proper place
usb: hub: Simplify error and success path in port_over_current_notify
usb: cdns3: allocate TX FIFO size according to composite EP number
usb: dwc3: Fix ep0 handling when getting reset while doing control transfer
usb: Probe EHCI, OHCI controllers asynchronously
usb: isp1760: Fix out-of-bounds array access
xhci: Don't defer primary roothub registration if there is only one roothub
USB: serial: option: add Quectel BG95 modem
USB: serial: pl2303: fix type detection for odd device
xhci: Allow host runtime PM as default for Intel Alder Lake N xHCI
xhci: Remove quirk for over 10 year old evaluation hardware
xhci: prevent U2 link power state if Intel tier policy prevented U1
xhci: use generic command timer for stop endpoint commands.
usb: host: xhci-plat: omit shared hcd if either root hub has no ports
usb: host: xhci-plat: prepare operation w/o shared hcd
usb: host: xhci-plat: create shared hcd after having added main hcd
xhci: prepare for operation w/o shared hcd
xhci: factor out parts of xhci_gen_setup()
...
695 lines
18 KiB
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695 lines
18 KiB
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2015, The Linux Foundation. All rights reserved.
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*/
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/dts-v1/;
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#include <dt-bindings/clock/qcom,gcc-ipq4019.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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model = "Qualcomm Technologies, Inc. IPQ4019";
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compatible = "qcom,ipq4019";
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interrupt-parent = <&intc>;
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reserved-memory {
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#address-cells = <0x1>;
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#size-cells = <0x1>;
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ranges;
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smem_region: smem@87e00000 {
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reg = <0x87e00000 0x080000>;
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no-map;
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};
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tz@87e80000 {
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reg = <0x87e80000 0x180000>;
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no-map;
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};
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};
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aliases {
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spi0 = &blsp1_spi1;
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spi1 = &blsp1_spi2;
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i2c0 = &blsp1_i2c3;
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i2c1 = &blsp1_i2c4;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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enable-method = "qcom,kpss-acc-v2";
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next-level-cache = <&L2>;
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qcom,acc = <&acc0>;
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qcom,saw = <&saw0>;
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reg = <0x0>;
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clocks = <&gcc GCC_APPS_CLK_SRC>;
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clock-frequency = <0>;
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clock-latency = <256000>;
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operating-points-v2 = <&cpu0_opp_table>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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enable-method = "qcom,kpss-acc-v2";
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next-level-cache = <&L2>;
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qcom,acc = <&acc1>;
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qcom,saw = <&saw1>;
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reg = <0x1>;
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clocks = <&gcc GCC_APPS_CLK_SRC>;
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clock-frequency = <0>;
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clock-latency = <256000>;
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operating-points-v2 = <&cpu0_opp_table>;
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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enable-method = "qcom,kpss-acc-v2";
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next-level-cache = <&L2>;
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qcom,acc = <&acc2>;
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qcom,saw = <&saw2>;
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reg = <0x2>;
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clocks = <&gcc GCC_APPS_CLK_SRC>;
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clock-frequency = <0>;
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clock-latency = <256000>;
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operating-points-v2 = <&cpu0_opp_table>;
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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enable-method = "qcom,kpss-acc-v2";
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next-level-cache = <&L2>;
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qcom,acc = <&acc3>;
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qcom,saw = <&saw3>;
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reg = <0x3>;
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clocks = <&gcc GCC_APPS_CLK_SRC>;
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clock-frequency = <0>;
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clock-latency = <256000>;
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operating-points-v2 = <&cpu0_opp_table>;
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};
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L2: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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qcom,saw = <&saw_l2>;
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};
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};
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cpu0_opp_table: opp_table0 {
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compatible = "operating-points-v2";
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opp-shared;
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opp-48000000 {
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opp-hz = /bits/ 64 <48000000>;
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clock-latency-ns = <256000>;
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};
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opp-200000000 {
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opp-hz = /bits/ 64 <200000000>;
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clock-latency-ns = <256000>;
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};
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opp-500000000 {
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opp-hz = /bits/ 64 <500000000>;
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clock-latency-ns = <256000>;
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};
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opp-716000000 {
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opp-hz = /bits/ 64 <716000000>;
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clock-latency-ns = <256000>;
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};
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};
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memory {
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device_type = "memory";
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reg = <0x0 0x0>;
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};
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pmu {
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compatible = "arm,cortex-a7-pmu";
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interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
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IRQ_TYPE_LEVEL_HIGH)>;
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};
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clocks {
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sleep_clk: sleep_clk {
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compatible = "fixed-clock";
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clock-frequency = <32000>;
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clock-output-names = "gcc_sleep_clk_src";
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#clock-cells = <0>;
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};
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xo: xo {
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compatible = "fixed-clock";
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clock-frequency = <48000000>;
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#clock-cells = <0>;
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};
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};
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firmware {
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scm {
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compatible = "qcom,scm-ipq4019";
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};
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <1 2 0xf08>,
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<1 3 0xf08>,
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<1 4 0xf08>,
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<1 1 0xf08>;
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clock-frequency = <48000000>;
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always-on;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "simple-bus";
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intc: interrupt-controller@b000000 {
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compatible = "qcom,msm-qgic2";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = <0x0b000000 0x1000>,
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<0x0b002000 0x1000>;
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};
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gcc: clock-controller@1800000 {
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compatible = "qcom,gcc-ipq4019";
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#clock-cells = <1>;
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#power-domain-cells = <1>;
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#reset-cells = <1>;
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reg = <0x1800000 0x60000>;
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};
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prng: rng@22000 {
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compatible = "qcom,prng";
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reg = <0x22000 0x140>;
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clocks = <&gcc GCC_PRNG_AHB_CLK>;
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clock-names = "core";
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status = "disabled";
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};
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tlmm: pinctrl@1000000 {
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compatible = "qcom,ipq4019-pinctrl";
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reg = <0x01000000 0x300000>;
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gpio-controller;
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gpio-ranges = <&tlmm 0 0 100>;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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};
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vqmmc: regulator@1948000 {
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compatible = "qcom,vqmmc-ipq4019-regulator";
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reg = <0x01948000 0x4>;
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regulator-name = "vqmmc";
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regulator-min-microvolt = <1500000>;
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regulator-max-microvolt = <3000000>;
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regulator-always-on;
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status = "disabled";
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};
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sdhci: sdhci@7824900 {
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compatible = "qcom,sdhci-msm-v4";
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reg = <0x7824900 0x11c>, <0x7824000 0x800>;
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interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "hc_irq", "pwr_irq";
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bus-width = <8>;
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clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>,
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<&gcc GCC_DCD_XO_CLK>;
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clock-names = "core", "iface", "xo";
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status = "disabled";
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};
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blsp_dma: dma-controller@7884000 {
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compatible = "qcom,bam-v1.7.0";
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reg = <0x07884000 0x23000>;
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interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "bam_clk";
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#dma-cells = <1>;
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qcom,ee = <0>;
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status = "disabled";
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};
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blsp1_spi1: spi@78b5000 { /* BLSP1 QUP1 */
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compatible = "qcom,spi-qup-v2.2.1";
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reg = <0x78b5000 0x600>;
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interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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#address-cells = <1>;
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#size-cells = <0>;
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dmas = <&blsp_dma 4>, <&blsp_dma 5>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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blsp1_spi2: spi@78b6000 { /* BLSP1 QUP2 */
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compatible = "qcom,spi-qup-v2.2.1";
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reg = <0x78b6000 0x600>;
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interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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#address-cells = <1>;
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#size-cells = <0>;
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dmas = <&blsp_dma 6>, <&blsp_dma 7>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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blsp1_i2c3: i2c@78b7000 { /* BLSP1 QUP3 */
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compatible = "qcom,i2c-qup-v2.2.1";
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reg = <0x78b7000 0x600>;
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interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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#address-cells = <1>;
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#size-cells = <0>;
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dmas = <&blsp_dma 8>, <&blsp_dma 9>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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blsp1_i2c4: i2c@78b8000 { /* BLSP1 QUP4 */
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compatible = "qcom,i2c-qup-v2.2.1";
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reg = <0x78b8000 0x600>;
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interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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#address-cells = <1>;
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#size-cells = <0>;
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dmas = <&blsp_dma 10>, <&blsp_dma 11>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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cryptobam: dma-controller@8e04000 {
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compatible = "qcom,bam-v1.7.0";
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reg = <0x08e04000 0x20000>;
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interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
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clock-names = "bam_clk";
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#dma-cells = <1>;
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qcom,ee = <1>;
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qcom,controlled-remotely;
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status = "disabled";
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};
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crypto: crypto@8e3a000 {
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compatible = "qcom,crypto-v5.1";
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reg = <0x08e3a000 0x6000>;
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clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
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<&gcc GCC_CRYPTO_AXI_CLK>,
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<&gcc GCC_CRYPTO_CLK>;
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clock-names = "iface", "bus", "core";
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dmas = <&cryptobam 2>, <&cryptobam 3>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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acc0: clock-controller@b088000 {
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compatible = "qcom,kpss-acc-v2";
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reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
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};
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acc1: clock-controller@b098000 {
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compatible = "qcom,kpss-acc-v2";
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reg = <0x0b098000 0x1000>, <0xb008000 0x1000>;
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};
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acc2: clock-controller@b0a8000 {
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compatible = "qcom,kpss-acc-v2";
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reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>;
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};
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acc3: clock-controller@b0b8000 {
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compatible = "qcom,kpss-acc-v2";
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reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
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};
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saw0: regulator@b089000 {
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compatible = "qcom,saw2";
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reg = <0x0b089000 0x1000>, <0x0b009000 0x1000>;
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regulator;
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};
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saw1: regulator@b099000 {
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compatible = "qcom,saw2";
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reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>;
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regulator;
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};
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saw2: regulator@b0a9000 {
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compatible = "qcom,saw2";
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reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>;
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regulator;
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};
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saw3: regulator@b0b9000 {
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compatible = "qcom,saw2";
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reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>;
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regulator;
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};
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saw_l2: regulator@b012000 {
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compatible = "qcom,saw2";
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reg = <0xb012000 0x1000>;
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regulator;
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};
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blsp1_uart1: serial@78af000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0x78af000 0x200>;
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interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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dmas = <&blsp_dma 0>, <&blsp_dma 1>;
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dma-names = "tx", "rx";
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};
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blsp1_uart2: serial@78b0000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0x78b0000 0x200>;
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interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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dmas = <&blsp_dma 2>, <&blsp_dma 3>;
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dma-names = "tx", "rx";
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};
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watchdog: watchdog@b017000 {
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compatible = "qcom,kpss-wdt", "qcom,kpss-wdt-ipq4019";
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reg = <0xb017000 0x40>;
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clocks = <&sleep_clk>;
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timeout-sec = <10>;
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status = "disabled";
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};
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restart@4ab000 {
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compatible = "qcom,pshold";
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reg = <0x4ab000 0x4>;
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};
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pcie0: pci@40000000 {
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compatible = "qcom,pcie-ipq4019", "snps,dw-pcie";
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reg = <0x40000000 0xf1d
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0x40000f20 0xa8
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0x80000 0x2000
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0x40100000 0x1000>;
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reg-names = "dbi", "elbi", "parf", "config";
|
|
device_type = "pci";
|
|
linux,pci-domain = <0>;
|
|
bus-range = <0x00 0xff>;
|
|
num-lanes = <1>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
|
|
ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000>,
|
|
<0x82000000 0 0x40300000 0x40300000 0 0x00d00000>;
|
|
|
|
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "msi";
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 0x7>;
|
|
interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
|
|
<0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
|
|
<0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
|
|
<0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
|
|
clocks = <&gcc GCC_PCIE_AHB_CLK>,
|
|
<&gcc GCC_PCIE_AXI_M_CLK>,
|
|
<&gcc GCC_PCIE_AXI_S_CLK>;
|
|
clock-names = "aux",
|
|
"master_bus",
|
|
"slave_bus";
|
|
|
|
resets = <&gcc PCIE_AXI_M_ARES>,
|
|
<&gcc PCIE_AXI_S_ARES>,
|
|
<&gcc PCIE_PIPE_ARES>,
|
|
<&gcc PCIE_AXI_M_VMIDMT_ARES>,
|
|
<&gcc PCIE_AXI_S_XPU_ARES>,
|
|
<&gcc PCIE_PARF_XPU_ARES>,
|
|
<&gcc PCIE_PHY_ARES>,
|
|
<&gcc PCIE_AXI_M_STICKY_ARES>,
|
|
<&gcc PCIE_PIPE_STICKY_ARES>,
|
|
<&gcc PCIE_PWR_ARES>,
|
|
<&gcc PCIE_AHB_ARES>,
|
|
<&gcc PCIE_PHY_AHB_ARES>;
|
|
reset-names = "axi_m",
|
|
"axi_s",
|
|
"pipe",
|
|
"axi_m_vmid",
|
|
"axi_s_xpu",
|
|
"parf",
|
|
"phy",
|
|
"axi_m_sticky",
|
|
"pipe_sticky",
|
|
"pwr",
|
|
"ahb",
|
|
"phy_ahb";
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
qpic_bam: dma-controller@7984000 {
|
|
compatible = "qcom,bam-v1.7.0";
|
|
reg = <0x7984000 0x1a000>;
|
|
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QPIC_CLK>;
|
|
clock-names = "bam_clk";
|
|
#dma-cells = <1>;
|
|
qcom,ee = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
nand: nand-controller@79b0000 {
|
|
compatible = "qcom,ipq4019-nand";
|
|
reg = <0x79b0000 0x1000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&gcc GCC_QPIC_CLK>,
|
|
<&gcc GCC_QPIC_AHB_CLK>;
|
|
clock-names = "core", "aon";
|
|
|
|
dmas = <&qpic_bam 0>,
|
|
<&qpic_bam 1>,
|
|
<&qpic_bam 2>;
|
|
dma-names = "tx", "rx", "cmd";
|
|
status = "disabled";
|
|
|
|
nand@0 {
|
|
reg = <0>;
|
|
|
|
nand-ecc-strength = <4>;
|
|
nand-ecc-step-size = <512>;
|
|
nand-bus-width = <8>;
|
|
};
|
|
};
|
|
|
|
wifi0: wifi@a000000 {
|
|
compatible = "qcom,ipq4019-wifi";
|
|
reg = <0xa000000 0x200000>;
|
|
resets = <&gcc WIFI0_CPU_INIT_RESET>,
|
|
<&gcc WIFI0_RADIO_SRIF_RESET>,
|
|
<&gcc WIFI0_RADIO_WARM_RESET>,
|
|
<&gcc WIFI0_RADIO_COLD_RESET>,
|
|
<&gcc WIFI0_CORE_WARM_RESET>,
|
|
<&gcc WIFI0_CORE_COLD_RESET>;
|
|
reset-names = "wifi_cpu_init", "wifi_radio_srif",
|
|
"wifi_radio_warm", "wifi_radio_cold",
|
|
"wifi_core_warm", "wifi_core_cold";
|
|
clocks = <&gcc GCC_WCSS2G_CLK>,
|
|
<&gcc GCC_WCSS2G_REF_CLK>,
|
|
<&gcc GCC_WCSS2G_RTC_CLK>;
|
|
clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
|
|
"wifi_wcss_rtc";
|
|
interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 38 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 39 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 40 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 41 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 42 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 43 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 44 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 45 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 46 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 47 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "msi0", "msi1", "msi2", "msi3",
|
|
"msi4", "msi5", "msi6", "msi7",
|
|
"msi8", "msi9", "msi10", "msi11",
|
|
"msi12", "msi13", "msi14", "msi15",
|
|
"legacy";
|
|
status = "disabled";
|
|
};
|
|
|
|
wifi1: wifi@a800000 {
|
|
compatible = "qcom,ipq4019-wifi";
|
|
reg = <0xa800000 0x200000>;
|
|
resets = <&gcc WIFI1_CPU_INIT_RESET>,
|
|
<&gcc WIFI1_RADIO_SRIF_RESET>,
|
|
<&gcc WIFI1_RADIO_WARM_RESET>,
|
|
<&gcc WIFI1_RADIO_COLD_RESET>,
|
|
<&gcc WIFI1_CORE_WARM_RESET>,
|
|
<&gcc WIFI1_CORE_COLD_RESET>;
|
|
reset-names = "wifi_cpu_init", "wifi_radio_srif",
|
|
"wifi_radio_warm", "wifi_radio_cold",
|
|
"wifi_core_warm", "wifi_core_cold";
|
|
clocks = <&gcc GCC_WCSS5G_CLK>,
|
|
<&gcc GCC_WCSS5G_REF_CLK>,
|
|
<&gcc GCC_WCSS5G_RTC_CLK>;
|
|
clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
|
|
"wifi_wcss_rtc";
|
|
interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 49 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 50 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 53 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 54 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 56 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 57 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 58 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 59 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 60 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 61 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 62 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 63 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "msi0", "msi1", "msi2", "msi3",
|
|
"msi4", "msi5", "msi6", "msi7",
|
|
"msi8", "msi9", "msi10", "msi11",
|
|
"msi12", "msi13", "msi14", "msi15",
|
|
"legacy";
|
|
status = "disabled";
|
|
};
|
|
|
|
mdio: mdio@90000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "qcom,ipq4019-mdio";
|
|
reg = <0x90000 0x64>;
|
|
status = "disabled";
|
|
|
|
ethphy0: ethernet-phy@0 {
|
|
reg = <0>;
|
|
};
|
|
|
|
ethphy1: ethernet-phy@1 {
|
|
reg = <1>;
|
|
};
|
|
|
|
ethphy2: ethernet-phy@2 {
|
|
reg = <2>;
|
|
};
|
|
|
|
ethphy3: ethernet-phy@3 {
|
|
reg = <3>;
|
|
};
|
|
|
|
ethphy4: ethernet-phy@4 {
|
|
reg = <4>;
|
|
};
|
|
};
|
|
|
|
usb3_ss_phy: ssphy@9a000 {
|
|
compatible = "qcom,usb-ss-ipq4019-phy";
|
|
#phy-cells = <0>;
|
|
reg = <0x9a000 0x800>;
|
|
reg-names = "phy_base";
|
|
resets = <&gcc USB3_UNIPHY_PHY_ARES>;
|
|
reset-names = "por_rst";
|
|
status = "disabled";
|
|
};
|
|
|
|
usb3_hs_phy: hsphy@a6000 {
|
|
compatible = "qcom,usb-hs-ipq4019-phy";
|
|
#phy-cells = <0>;
|
|
reg = <0xa6000 0x40>;
|
|
reg-names = "phy_base";
|
|
resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>;
|
|
reset-names = "por_rst", "srif_rst";
|
|
status = "disabled";
|
|
};
|
|
|
|
usb3: usb3@8af8800 {
|
|
compatible = "qcom,ipq4019-dwc3", "qcom,dwc3";
|
|
reg = <0x8af8800 0x100>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
clocks = <&gcc GCC_USB3_MASTER_CLK>,
|
|
<&gcc GCC_USB3_SLEEP_CLK>,
|
|
<&gcc GCC_USB3_MOCK_UTMI_CLK>;
|
|
clock-names = "core", "sleep", "mock_utmi";
|
|
ranges;
|
|
status = "disabled";
|
|
|
|
dwc3@8a00000 {
|
|
compatible = "snps,dwc3";
|
|
reg = <0x8a00000 0xf8000>;
|
|
interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
|
|
phys = <&usb3_hs_phy>, <&usb3_ss_phy>;
|
|
phy-names = "usb2-phy", "usb3-phy";
|
|
dr_mode = "host";
|
|
};
|
|
};
|
|
|
|
usb2_hs_phy: hsphy@a8000 {
|
|
compatible = "qcom,usb-hs-ipq4019-phy";
|
|
#phy-cells = <0>;
|
|
reg = <0xa8000 0x40>;
|
|
reg-names = "phy_base";
|
|
resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>;
|
|
reset-names = "por_rst", "srif_rst";
|
|
status = "disabled";
|
|
};
|
|
|
|
usb2: usb2@60f8800 {
|
|
compatible = "qcom,ipq4019-dwc3", "qcom,dwc3";
|
|
reg = <0x60f8800 0x100>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
clocks = <&gcc GCC_USB2_MASTER_CLK>,
|
|
<&gcc GCC_USB2_SLEEP_CLK>,
|
|
<&gcc GCC_USB2_MOCK_UTMI_CLK>;
|
|
clock-names = "master", "sleep", "mock_utmi";
|
|
ranges;
|
|
status = "disabled";
|
|
|
|
dwc3@6000000 {
|
|
compatible = "snps,dwc3";
|
|
reg = <0x6000000 0xf8000>;
|
|
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
|
|
phys = <&usb2_hs_phy>;
|
|
phy-names = "usb2-phy";
|
|
dr_mode = "host";
|
|
};
|
|
};
|
|
};
|
|
};
|