2bcb9c2508
After getting the regmap size from the device tree we should reduce the ranges to the really available registers. This allows to read only existing registers from the debug fs and makes the regmap check out-of-bounds access. For the jz4780 we have done this already. Suggested-for: Paul Cercueil <paul@crapouillou.net> Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
378 lines
7.4 KiB
Text
378 lines
7.4 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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#include <dt-bindings/clock/ingenic,jz4725b-cgu.h>
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#include <dt-bindings/clock/ingenic,tcu.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "ingenic,jz4725b";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "ingenic,xburst-mxu1.0";
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reg = <0>;
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clocks = <&cgu JZ4725B_CLK_CCLK>;
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clock-names = "cpu";
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};
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};
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cpuintc: interrupt-controller {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "mti,cpu-interrupt-controller";
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};
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intc: interrupt-controller@10001000 {
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compatible = "ingenic,jz4725b-intc", "ingenic,jz4740-intc";
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reg = <0x10001000 0x14>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&cpuintc>;
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interrupts = <2>;
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};
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ext: ext {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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};
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osc32k: osc32k {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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};
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cgu: clock-controller@10000000 {
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compatible = "ingenic,jz4725b-cgu";
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reg = <0x10000000 0x100>;
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clocks = <&ext>, <&osc32k>;
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clock-names = "ext", "osc32k";
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#clock-cells = <1>;
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};
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tcu: timer@10002000 {
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compatible = "ingenic,jz4725b-tcu", "simple-mfd";
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reg = <0x10002000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x10002000 0x1000>;
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#clock-cells = <1>;
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clocks = <&cgu JZ4725B_CLK_RTC>,
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<&cgu JZ4725B_CLK_EXT>,
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<&cgu JZ4725B_CLK_PCLK>,
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<&cgu JZ4725B_CLK_TCU>;
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clock-names = "rtc", "ext", "pclk", "tcu";
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&intc>;
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interrupts = <23>, <22>, <21>;
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watchdog: watchdog@0 {
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compatible = "ingenic,jz4725b-watchdog", "ingenic,jz4740-watchdog";
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reg = <0x0 0xc>;
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clocks = <&tcu TCU_CLK_WDT>;
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clock-names = "wdt";
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};
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pwm: pwm@60 {
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compatible = "ingenic,jz4725b-pwm";
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reg = <0x60 0x40>;
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#pwm-cells = <3>;
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clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
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<&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_TIMER3>,
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<&tcu TCU_CLK_TIMER4>, <&tcu TCU_CLK_TIMER5>;
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clock-names = "timer0", "timer1", "timer2",
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"timer3", "timer4", "timer5";
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};
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ost: timer@e0 {
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compatible = "ingenic,jz4725b-ost";
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reg = <0xe0 0x20>;
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clocks = <&tcu TCU_CLK_OST>;
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clock-names = "ost";
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interrupts = <15>;
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};
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};
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rtc_dev: rtc@10003000 {
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compatible = "ingenic,jz4725b-rtc", "ingenic,jz4740-rtc";
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reg = <0x10003000 0x40>;
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interrupt-parent = <&intc>;
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interrupts = <6>;
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clocks = <&cgu JZ4725B_CLK_RTC>;
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clock-names = "rtc";
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};
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pinctrl: pinctrl@10010000 {
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compatible = "ingenic,jz4725b-pinctrl";
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reg = <0x10010000 0x400>;
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#address-cells = <1>;
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#size-cells = <0>;
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gpa: gpio@0 {
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compatible = "ingenic,jz4725b-gpio";
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reg = <0>;
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gpio-controller;
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gpio-ranges = <&pinctrl 0 0 32>;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&intc>;
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interrupts = <16>;
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};
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gpb: gpio@1 {
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compatible = "ingenic,jz4725b-gpio";
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reg = <1>;
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gpio-controller;
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gpio-ranges = <&pinctrl 0 32 32>;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&intc>;
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interrupts = <15>;
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};
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gpc: gpio@2 {
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compatible = "ingenic,jz4725b-gpio";
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reg = <2>;
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gpio-controller;
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gpio-ranges = <&pinctrl 0 64 32>;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&intc>;
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interrupts = <14>;
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};
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gpd: gpio@3 {
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compatible = "ingenic,jz4725b-gpio";
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reg = <3>;
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gpio-controller;
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gpio-ranges = <&pinctrl 0 96 32>;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&intc>;
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interrupts = <13>;
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};
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};
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aic: audio-controller@10020000 {
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compatible = "ingenic,jz4725b-i2s", "ingenic,jz4740-i2s";
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reg = <0x10020000 0x38>;
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#sound-dai-cells = <0>;
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clocks = <&cgu JZ4725B_CLK_AIC>,
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<&cgu JZ4725B_CLK_I2S>,
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<&cgu JZ4725B_CLK_EXT>,
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<&cgu JZ4725B_CLK_PLL_HALF>;
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clock-names = "aic", "i2s", "ext", "pll half";
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interrupt-parent = <&intc>;
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interrupts = <10>;
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dmas = <&dmac 25 0xffffffff>, <&dmac 24 0xffffffff>;
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dma-names = "rx", "tx";
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};
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codec: audio-codec@100200a4 {
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compatible = "ingenic,jz4725b-codec";
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reg = <0x100200a4 0x8>;
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#sound-dai-cells = <0>;
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clocks = <&cgu JZ4725B_CLK_AIC>;
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clock-names = "aic";
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};
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mmc0: mmc@10021000 {
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compatible = "ingenic,jz4725b-mmc";
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reg = <0x10021000 0x1000>;
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clocks = <&cgu JZ4725B_CLK_MMC0>;
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clock-names = "mmc";
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interrupt-parent = <&intc>;
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interrupts = <25>;
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dmas = <&dmac 27 0xffffffff>, <&dmac 26 0xffffffff>;
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dma-names = "rx", "tx";
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cap-sd-highspeed;
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cap-mmc-highspeed;
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cap-sdio-irq;
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};
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mmc1: mmc@10022000 {
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compatible = "ingenic,jz4725b-mmc";
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reg = <0x10022000 0x1000>;
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clocks = <&cgu JZ4725B_CLK_MMC1>;
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clock-names = "mmc";
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interrupt-parent = <&intc>;
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interrupts = <24>;
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dmas = <&dmac 31 0xffffffff>, <&dmac 30 0xffffffff>;
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dma-names = "rx", "tx";
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cap-sd-highspeed;
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cap-mmc-highspeed;
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cap-sdio-irq;
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};
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uart: serial@10030000 {
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compatible = "ingenic,jz4725b-uart", "ingenic,jz4740-uart";
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reg = <0x10030000 0x100>;
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interrupt-parent = <&intc>;
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interrupts = <9>;
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clocks = <&ext>, <&cgu JZ4725B_CLK_UART>;
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clock-names = "baud", "module";
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};
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adc: adc@10070000 {
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compatible = "ingenic,jz4725b-adc";
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#io-channel-cells = <1>;
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reg = <0x10070000 0x30>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x10070000 0x30>;
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clocks = <&cgu JZ4725B_CLK_ADC>;
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clock-names = "adc";
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interrupt-parent = <&intc>;
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interrupts = <18>;
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};
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nemc: memory-controller@13010000 {
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compatible = "ingenic,jz4725b-nemc", "ingenic,jz4740-nemc";
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reg = <0x13010000 0x10000>;
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <1 0 0x18000000 0x4000000>, <2 0 0x14000000 0x4000000>,
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<3 0 0x0c000000 0x4000000>, <4 0 0x08000000 0x4000000>;
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clocks = <&cgu JZ4725B_CLK_MCLK>;
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};
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dmac: dma-controller@13020000 {
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compatible = "ingenic,jz4725b-dma";
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reg = <0x13020000 0xd8>, <0x13020300 0x14>;
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#dma-cells = <2>;
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interrupt-parent = <&intc>;
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interrupts = <29>;
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clocks = <&cgu JZ4725B_CLK_DMA>;
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};
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udc: usb@13040000 {
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compatible = "ingenic,jz4725b-musb", "ingenic,jz4740-musb";
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reg = <0x13040000 0x10000>;
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interrupt-parent = <&intc>;
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interrupts = <27>;
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interrupt-names = "mc";
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clocks = <&cgu JZ4725B_CLK_UDC>;
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clock-names = "udc";
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};
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lcd: lcd-controller@13050000 {
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compatible = "ingenic,jz4725b-lcd";
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reg = <0x13050000 0x130>; /* tbc */
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interrupt-parent = <&intc>;
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interrupts = <31>;
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clocks = <&cgu JZ4725B_CLK_LCD>;
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clock-names = "lcd_pclk";
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lcd_ports: ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@8 {
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reg = <8>;
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ipu_output: endpoint {
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remote-endpoint = <&ipu_input>;
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};
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};
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};
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};
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ipu: ipu@13080000 {
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compatible = "ingenic,jz4725b-ipu";
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reg = <0x13080000 0x64>;
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interrupt-parent = <&intc>;
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interrupts = <30>;
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clocks = <&cgu JZ4725B_CLK_IPU>;
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clock-names = "ipu";
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port {
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ipu_input: endpoint {
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remote-endpoint = <&ipu_output>;
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};
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};
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};
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bch: ecc-controller@130d0000 {
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compatible = "ingenic,jz4725b-bch";
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reg = <0x130d0000 0x44>;
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clocks = <&cgu JZ4725B_CLK_BCH>;
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};
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rom: memory@1fc00000 {
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compatible = "mtd-rom";
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probe-type = "map_rom";
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reg = <0x1fc00000 0x2000>;
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bank-width = <4>;
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device-width = <1>;
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};
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};
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