8b356e536e
commit72f2ecb7ec("ACPI: bus: Set CPPC _OSC bits for all and when CPPC_LIB is supported") added support for claiming to support CPPC in _OSC on non-Intel platforms. This unfortunately caused a regression on a vartiety of AMD platforms in the field because a number of AMD platforms don't set the `_OSC` bit 5 or 6 to indicate CPPC or CPPC v2 support. As these AMD platforms already claim CPPC support via a dedicated MSR from `X86_FEATURE_CPPC`, use this enable this feature rather than requiring the `_OSC` on platforms with a dedicated MSR. If there is additional breakage on the shared memory designs also missing this _OSC, additional follow up changes may be needed. Fixes:72f2ecb7ec("Set CPPC _OSC bits for all and when CPPC_LIB is supported") Reported-by: Perry Yuan <perry.yuan@amd.com> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
112 lines
2.3 KiB
C
112 lines
2.3 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* cppc.c: CPPC Interface for x86
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* Copyright (c) 2016, Intel Corporation.
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*/
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#include <acpi/cppc_acpi.h>
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#include <asm/msr.h>
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#include <asm/processor.h>
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#include <asm/topology.h>
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/* Refer to drivers/acpi/cppc_acpi.c for the description of functions */
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bool cpc_supported_by_cpu(void)
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{
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switch (boot_cpu_data.x86_vendor) {
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case X86_VENDOR_AMD:
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case X86_VENDOR_HYGON:
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return boot_cpu_has(X86_FEATURE_CPPC);
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}
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return false;
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}
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bool cpc_ffh_supported(void)
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{
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return true;
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}
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int cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *val)
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{
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int err;
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err = rdmsrl_safe_on_cpu(cpunum, reg->address, val);
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if (!err) {
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u64 mask = GENMASK_ULL(reg->bit_offset + reg->bit_width - 1,
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reg->bit_offset);
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*val &= mask;
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*val >>= reg->bit_offset;
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}
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return err;
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}
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int cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val)
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{
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u64 rd_val;
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int err;
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err = rdmsrl_safe_on_cpu(cpunum, reg->address, &rd_val);
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if (!err) {
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u64 mask = GENMASK_ULL(reg->bit_offset + reg->bit_width - 1,
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reg->bit_offset);
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val <<= reg->bit_offset;
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val &= mask;
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rd_val &= ~mask;
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rd_val |= val;
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err = wrmsrl_safe_on_cpu(cpunum, reg->address, rd_val);
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}
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return err;
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}
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static void amd_set_max_freq_ratio(void)
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{
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struct cppc_perf_caps perf_caps;
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u64 highest_perf, nominal_perf;
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u64 perf_ratio;
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int rc;
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rc = cppc_get_perf_caps(0, &perf_caps);
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if (rc) {
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pr_debug("Could not retrieve perf counters (%d)\n", rc);
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return;
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}
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highest_perf = amd_get_highest_perf();
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nominal_perf = perf_caps.nominal_perf;
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if (!highest_perf || !nominal_perf) {
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pr_debug("Could not retrieve highest or nominal performance\n");
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return;
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}
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perf_ratio = div_u64(highest_perf * SCHED_CAPACITY_SCALE, nominal_perf);
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/* midpoint between max_boost and max_P */
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perf_ratio = (perf_ratio + SCHED_CAPACITY_SCALE) >> 1;
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if (!perf_ratio) {
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pr_debug("Non-zero highest/nominal perf values led to a 0 ratio\n");
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return;
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}
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freq_invariance_set_perf_ratio(perf_ratio, false);
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}
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static DEFINE_MUTEX(freq_invariance_lock);
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void init_freq_invariance_cppc(void)
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{
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static bool init_done;
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if (!cpu_feature_enabled(X86_FEATURE_APERFMPERF))
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return;
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if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
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return;
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mutex_lock(&freq_invariance_lock);
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if (!init_done)
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amd_set_max_freq_ratio();
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init_done = true;
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mutex_unlock(&freq_invariance_lock);
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}
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