837d542a09
Instead of centralizing all headers in the same folder. Separate them into different folders and place them among those source files those who really need them. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
886 lines
24 KiB
C
886 lines
24 KiB
C
/*
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* Copyright 2017 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef SMU75_DISCRETE_H
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#define SMU75_DISCRETE_H
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#include "smu75.h"
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#pragma pack(push, 1)
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#define NUM_SCLK_RANGE 8
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#define VCO_3_6 1
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#define VCO_2_4 3
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#define POSTDIV_DIV_BY_1 0
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#define POSTDIV_DIV_BY_2 1
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#define POSTDIV_DIV_BY_4 2
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#define POSTDIV_DIV_BY_8 3
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#define POSTDIV_DIV_BY_16 4
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struct sclkFcwRange_t {
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uint8_t vco_setting; /* 1: 3-6GHz, 3: 2-4GHz */
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uint8_t postdiv; /* divide by 2^n */
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uint16_t fcw_pcc;
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uint16_t fcw_trans_upper;
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uint16_t fcw_trans_lower;
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};
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typedef struct sclkFcwRange_t sclkFcwRange_t;
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struct SMIO_Pattern {
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uint16_t Voltage;
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uint8_t Smio;
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uint8_t padding;
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};
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typedef struct SMIO_Pattern SMIO_Pattern;
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struct SMIO_Table {
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SMIO_Pattern Pattern[SMU_MAX_SMIO_LEVELS];
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};
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typedef struct SMIO_Table SMIO_Table;
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struct SMU_SclkSetting {
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uint32_t SclkFrequency;
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uint16_t Fcw_int;
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uint16_t Fcw_frac;
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uint16_t Pcc_fcw_int;
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uint8_t PllRange;
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uint8_t SSc_En;
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uint16_t Sclk_slew_rate;
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uint16_t Pcc_up_slew_rate;
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uint16_t Pcc_down_slew_rate;
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uint16_t Fcw1_int;
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uint16_t Fcw1_frac;
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uint16_t Sclk_ss_slew_rate;
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};
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typedef struct SMU_SclkSetting SMU_SclkSetting;
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struct SMU75_Discrete_GraphicsLevel {
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SMU_VoltageLevel MinVoltage;
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uint8_t pcieDpmLevel;
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uint8_t DeepSleepDivId;
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uint16_t ActivityLevel;
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uint32_t CgSpllFuncCntl3;
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uint32_t CgSpllFuncCntl4;
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uint32_t CcPwrDynRm;
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uint32_t CcPwrDynRm1;
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uint8_t SclkDid;
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uint8_t padding;
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uint8_t EnabledForActivity;
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uint8_t EnabledForThrottle;
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uint8_t UpHyst;
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uint8_t DownHyst;
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uint8_t VoltageDownHyst;
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uint8_t PowerThrottle;
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SMU_SclkSetting SclkSetting;
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uint8_t ScksStretchThreshVid[NUM_SCKS_STATE_TYPES];
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uint16_t Padding;
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};
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typedef struct SMU75_Discrete_GraphicsLevel SMU75_Discrete_GraphicsLevel;
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struct SMU75_Discrete_ACPILevel {
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uint32_t Flags;
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SMU_VoltageLevel MinVoltage;
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uint32_t SclkFrequency;
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uint8_t SclkDid;
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uint8_t DisplayWatermark;
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uint8_t DeepSleepDivId;
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uint8_t padding;
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uint32_t CcPwrDynRm;
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uint32_t CcPwrDynRm1;
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SMU_SclkSetting SclkSetting;
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};
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typedef struct SMU75_Discrete_ACPILevel SMU75_Discrete_ACPILevel;
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struct SMU75_Discrete_Ulv {
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uint32_t CcPwrDynRm;
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uint32_t CcPwrDynRm1;
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uint16_t VddcOffset;
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uint8_t VddcOffsetVid;
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uint8_t VddcPhase;
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uint16_t BifSclkDfs;
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uint16_t Reserved;
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};
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typedef struct SMU75_Discrete_Ulv SMU75_Discrete_Ulv;
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struct SMU75_Discrete_MemoryLevel {
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SMU_VoltageLevel MinVoltage;
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uint32_t MinMvdd;
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uint32_t MclkFrequency;
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uint8_t StutterEnable;
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uint8_t EnabledForThrottle;
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uint8_t EnabledForActivity;
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uint8_t padding_0;
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uint8_t UpHyst;
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uint8_t DownHyst;
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uint8_t VoltageDownHyst;
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uint8_t padding_1;
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uint16_t ActivityLevel;
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uint8_t DisplayWatermark;
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uint8_t padding_2;
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uint16_t Fcw_int;
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uint16_t Fcw_frac;
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uint8_t Postdiv;
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uint8_t padding_3[3];
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};
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typedef struct SMU75_Discrete_MemoryLevel SMU75_Discrete_MemoryLevel;
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struct SMU75_Discrete_LinkLevel {
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uint8_t PcieGenSpeed;
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uint8_t PcieLaneCount;
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uint8_t EnabledForActivity;
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uint8_t SPC;
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uint32_t DownThreshold;
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uint32_t UpThreshold;
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uint16_t BifSclkDfs;
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uint16_t Reserved;
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};
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typedef struct SMU75_Discrete_LinkLevel SMU75_Discrete_LinkLevel;
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/* MC ARB DRAM Timing registers. */
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struct SMU75_Discrete_MCArbDramTimingTableEntry {
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uint32_t McArbDramTiming;
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uint32_t McArbDramTiming2;
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uint32_t McArbBurstTime;
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uint32_t McArbRfshRate;
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uint32_t McArbMisc3;
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};
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typedef struct SMU75_Discrete_MCArbDramTimingTableEntry SMU75_Discrete_MCArbDramTimingTableEntry;
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struct SMU75_Discrete_MCArbDramTimingTable {
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SMU75_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
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};
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typedef struct SMU75_Discrete_MCArbDramTimingTable SMU75_Discrete_MCArbDramTimingTable;
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/* UVD VCLK/DCLK state (level) definition. */
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struct SMU75_Discrete_UvdLevel {
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uint32_t VclkFrequency;
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uint32_t DclkFrequency;
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SMU_VoltageLevel MinVoltage;
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uint8_t VclkDivider;
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uint8_t DclkDivider;
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uint8_t padding[2];
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};
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typedef struct SMU75_Discrete_UvdLevel SMU75_Discrete_UvdLevel;
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/* Clocks for other external blocks (VCE, ACP, SAMU). */
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struct SMU75_Discrete_ExtClkLevel {
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uint32_t Frequency;
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SMU_VoltageLevel MinVoltage;
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uint8_t Divider;
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uint8_t padding[3];
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};
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typedef struct SMU75_Discrete_ExtClkLevel SMU75_Discrete_ExtClkLevel;
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struct SMU75_Discrete_StateInfo {
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uint32_t SclkFrequency;
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uint32_t MclkFrequency;
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uint32_t VclkFrequency;
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uint32_t DclkFrequency;
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uint32_t SamclkFrequency;
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uint32_t AclkFrequency;
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uint32_t EclkFrequency;
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uint16_t MvddVoltage;
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uint16_t padding16;
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uint8_t DisplayWatermark;
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uint8_t McArbIndex;
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uint8_t McRegIndex;
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uint8_t SeqIndex;
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uint8_t SclkDid;
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int8_t SclkIndex;
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int8_t MclkIndex;
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uint8_t PCIeGen;
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};
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typedef struct SMU75_Discrete_StateInfo SMU75_Discrete_StateInfo;
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struct SMU75_Discrete_DpmTable {
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SMU75_PIDController GraphicsPIDController;
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SMU75_PIDController MemoryPIDController;
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SMU75_PIDController LinkPIDController;
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uint32_t SystemFlags;
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uint32_t VRConfig;
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uint32_t SmioMask1;
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uint32_t SmioMask2;
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SMIO_Table SmioTable1;
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SMIO_Table SmioTable2;
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uint32_t MvddLevelCount;
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uint8_t BapmVddcVidHiSidd [SMU75_MAX_LEVELS_VDDC];
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uint8_t BapmVddcVidLoSidd [SMU75_MAX_LEVELS_VDDC];
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uint8_t BapmVddcVidHiSidd2 [SMU75_MAX_LEVELS_VDDC];
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uint8_t GraphicsDpmLevelCount;
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uint8_t MemoryDpmLevelCount;
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uint8_t LinkLevelCount;
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uint8_t MasterDeepSleepControl;
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uint8_t UvdLevelCount;
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uint8_t VceLevelCount;
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uint8_t AcpLevelCount;
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uint8_t SamuLevelCount;
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uint8_t ThermOutGpio;
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uint8_t ThermOutPolarity;
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uint8_t ThermOutMode;
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uint8_t BootPhases;
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uint8_t VRHotLevel;
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uint8_t LdoRefSel;
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uint8_t Reserved1[2];
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uint16_t FanStartTemperature;
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uint16_t FanStopTemperature;
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uint16_t MaxVoltage;
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uint16_t Reserved2;
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uint32_t Reserved;
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SMU75_Discrete_GraphicsLevel GraphicsLevel [SMU75_MAX_LEVELS_GRAPHICS];
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SMU75_Discrete_MemoryLevel MemoryACPILevel;
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SMU75_Discrete_MemoryLevel MemoryLevel [SMU75_MAX_LEVELS_MEMORY];
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SMU75_Discrete_LinkLevel LinkLevel [SMU75_MAX_LEVELS_LINK];
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SMU75_Discrete_ACPILevel ACPILevel;
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SMU75_Discrete_UvdLevel UvdLevel [SMU75_MAX_LEVELS_UVD];
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SMU75_Discrete_ExtClkLevel VceLevel [SMU75_MAX_LEVELS_VCE];
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SMU75_Discrete_ExtClkLevel AcpLevel [SMU75_MAX_LEVELS_ACP];
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SMU75_Discrete_ExtClkLevel SamuLevel [SMU75_MAX_LEVELS_SAMU];
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SMU75_Discrete_Ulv Ulv;
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uint8_t DisplayWatermark [SMU75_MAX_LEVELS_MEMORY][SMU75_MAX_LEVELS_GRAPHICS];
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uint32_t SclkStepSize;
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uint32_t Smio [SMU75_MAX_ENTRIES_SMIO];
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uint8_t UvdBootLevel;
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uint8_t VceBootLevel;
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uint8_t AcpBootLevel;
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uint8_t SamuBootLevel;
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uint8_t GraphicsBootLevel;
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uint8_t GraphicsVoltageChangeEnable;
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uint8_t GraphicsThermThrottleEnable;
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uint8_t GraphicsInterval;
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uint8_t VoltageInterval;
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uint8_t ThermalInterval;
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uint16_t TemperatureLimitHigh;
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uint16_t TemperatureLimitLow;
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uint8_t MemoryBootLevel;
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uint8_t MemoryVoltageChangeEnable;
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uint16_t BootMVdd;
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uint8_t MemoryInterval;
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uint8_t MemoryThermThrottleEnable;
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uint16_t VoltageResponseTime;
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uint16_t PhaseResponseTime;
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uint8_t PCIeBootLinkLevel;
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uint8_t PCIeGenInterval;
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uint8_t DTEInterval;
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uint8_t DTEMode;
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uint8_t SVI2Enable;
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uint8_t VRHotGpio;
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uint8_t AcDcGpio;
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uint8_t ThermGpio;
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uint16_t PPM_PkgPwrLimit;
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uint16_t PPM_TemperatureLimit;
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uint16_t DefaultTdp;
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uint16_t TargetTdp;
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uint16_t FpsHighThreshold;
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uint16_t FpsLowThreshold;
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uint16_t BAPMTI_R [SMU75_DTE_ITERATIONS][SMU75_DTE_SOURCES][SMU75_DTE_SINKS];
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uint16_t BAPMTI_RC [SMU75_DTE_ITERATIONS][SMU75_DTE_SOURCES][SMU75_DTE_SINKS];
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uint16_t TemperatureLimitEdge;
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uint16_t TemperatureLimitHotspot;
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uint16_t BootVddc;
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uint16_t BootVddci;
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uint16_t FanGainEdge;
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uint16_t FanGainHotspot;
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uint32_t LowSclkInterruptThreshold;
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uint32_t VddGfxReChkWait;
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uint8_t ClockStretcherAmount;
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uint8_t Sclk_CKS_masterEn0_7;
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uint8_t Sclk_CKS_masterEn8_15;
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uint8_t DPMFreezeAndForced;
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uint8_t Sclk_voltageOffset[8];
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SMU_ClockStretcherDataTable ClockStretcherDataTable;
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SMU_CKS_LOOKUPTable CKS_LOOKUPTable;
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uint32_t CurrSclkPllRange;
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sclkFcwRange_t SclkFcwRangeTable[NUM_SCLK_RANGE];
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GB_VDROOP_TABLE_t BTCGB_VDROOP_TABLE[BTCGB_VDROOP_TABLE_MAX_ENTRIES];
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SMU_QuadraticCoeffs AVFSGB_FUSE_TABLE[AVFSGB_VDROOP_TABLE_MAX_ENTRIES];
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};
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typedef struct SMU75_Discrete_DpmTable SMU75_Discrete_DpmTable;
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struct SMU75_Discrete_FanTable {
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uint16_t FdoMode;
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int16_t TempMin;
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int16_t TempMed;
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int16_t TempMax;
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int16_t Slope1;
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int16_t Slope2;
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int16_t FdoMin;
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int16_t HystUp;
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int16_t HystDown;
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int16_t HystSlope;
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int16_t TempRespLim;
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int16_t TempCurr;
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int16_t SlopeCurr;
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int16_t PwmCurr;
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uint32_t RefreshPeriod;
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int16_t FdoMax;
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uint8_t TempSrc;
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int8_t Padding;
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};
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typedef struct SMU75_Discrete_FanTable SMU75_Discrete_FanTable;
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#define SMU7_DISCRETE_GPIO_SCLK_DEBUG 4
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#define SMU7_DISCRETE_GPIO_SCLK_DEBUG_BIT (0x1 << SMU7_DISCRETE_GPIO_SCLK_DEBUG)
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struct SMU7_MclkDpmScoreboard {
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uint32_t PercentageBusy;
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int32_t PIDError;
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int32_t PIDIntegral;
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int32_t PIDOutput;
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uint32_t SigmaDeltaAccum;
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uint32_t SigmaDeltaOutput;
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uint32_t SigmaDeltaLevel;
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uint32_t UtilizationSetpoint;
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uint8_t TdpClampMode;
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uint8_t TdcClampMode;
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uint8_t ThermClampMode;
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uint8_t VoltageBusy;
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int8_t CurrLevel;
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int8_t TargLevel;
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uint8_t LevelChangeInProgress;
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uint8_t UpHyst;
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uint8_t DownHyst;
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uint8_t VoltageDownHyst;
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uint8_t DpmEnable;
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uint8_t DpmRunning;
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uint8_t DpmForce;
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uint8_t DpmForceLevel;
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uint8_t padding2;
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uint8_t McArbIndex;
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uint32_t MinimumPerfMclk;
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uint8_t AcpiReq;
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uint8_t AcpiAck;
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uint8_t MclkSwitchInProgress;
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uint8_t MclkSwitchCritical;
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uint8_t IgnoreVBlank;
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uint8_t TargetMclkIndex;
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uint8_t TargetMvddIndex;
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uint8_t MclkSwitchResult;
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uint16_t VbiFailureCount;
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uint8_t VbiWaitCounter;
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uint8_t EnabledLevelsChange;
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uint16_t LevelResidencyCounters [SMU75_MAX_LEVELS_MEMORY];
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uint16_t LevelSwitchCounters [SMU75_MAX_LEVELS_MEMORY];
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void (*TargetStateCalculator)(uint8_t);
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void (*SavedTargetStateCalculator)(uint8_t);
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uint16_t AutoDpmInterval;
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uint16_t AutoDpmRange;
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uint16_t VbiTimeoutCount;
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uint16_t MclkSwitchingTime;
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uint8_t fastSwitch;
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uint8_t Save_PIC_VDDGFX_EXIT;
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uint8_t Save_PIC_VDDGFX_ENTER;
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uint8_t VbiTimeout;
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uint32_t HbmTempRegBackup;
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};
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typedef struct SMU7_MclkDpmScoreboard SMU7_MclkDpmScoreboard;
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struct SMU7_UlvScoreboard {
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uint8_t EnterUlv;
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uint8_t ExitUlv;
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uint8_t UlvActive;
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uint8_t WaitingForUlv;
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uint8_t UlvEnable;
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uint8_t UlvRunning;
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uint8_t UlvMasterEnable;
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uint8_t padding;
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uint32_t UlvAbortedCount;
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uint32_t UlvTimeStamp;
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};
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typedef struct SMU7_UlvScoreboard SMU7_UlvScoreboard;
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struct VddgfxSavedRegisters {
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uint32_t GPU_DBG[3];
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uint32_t MEC_BaseAddress_Hi;
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|
uint32_t MEC_BaseAddress_Lo;
|
|
uint32_t THM_TMON0_CTRL2__RDIR_PRESENT;
|
|
uint32_t THM_TMON1_CTRL2__RDIR_PRESENT;
|
|
uint32_t CP_INT_CNTL;
|
|
};
|
|
|
|
typedef struct VddgfxSavedRegisters VddgfxSavedRegisters;
|
|
|
|
struct SMU7_VddGfxScoreboard {
|
|
uint8_t VddGfxEnable;
|
|
uint8_t VddGfxActive;
|
|
uint8_t VPUResetOccured;
|
|
uint8_t padding;
|
|
|
|
uint32_t VddGfxEnteredCount;
|
|
uint32_t VddGfxAbortedCount;
|
|
|
|
uint32_t VddGfxVid;
|
|
|
|
VddgfxSavedRegisters SavedRegisters;
|
|
};
|
|
|
|
typedef struct SMU7_VddGfxScoreboard SMU7_VddGfxScoreboard;
|
|
|
|
struct SMU7_TdcLimitScoreboard {
|
|
uint8_t Enable;
|
|
uint8_t Running;
|
|
uint16_t Alpha;
|
|
uint32_t FilteredIddc;
|
|
uint32_t IddcLimit;
|
|
uint32_t IddcHyst;
|
|
SMU7_HystController_Data HystControllerData;
|
|
};
|
|
|
|
typedef struct SMU7_TdcLimitScoreboard SMU7_TdcLimitScoreboard;
|
|
|
|
struct SMU7_PkgPwrLimitScoreboard {
|
|
uint8_t Enable;
|
|
uint8_t Running;
|
|
uint16_t Alpha;
|
|
uint32_t FilteredPkgPwr;
|
|
uint32_t Limit;
|
|
uint32_t Hyst;
|
|
uint32_t LimitFromDriver;
|
|
uint8_t PowerSharingEnabled;
|
|
uint8_t PowerSharingCounter;
|
|
uint8_t PowerSharingINTEnabled;
|
|
uint8_t GFXActivityCounterEnabled;
|
|
uint32_t EnergyCount;
|
|
uint32_t PSACTCount;
|
|
uint8_t RollOverRequired;
|
|
uint8_t RollOverCount;
|
|
uint8_t padding[2];
|
|
SMU7_HystController_Data HystControllerData;
|
|
};
|
|
|
|
typedef struct SMU7_PkgPwrLimitScoreboard SMU7_PkgPwrLimitScoreboard;
|
|
|
|
struct SMU7_BapmScoreboard {
|
|
uint32_t source_powers[SMU75_DTE_SOURCES];
|
|
uint32_t source_powers_last[SMU75_DTE_SOURCES];
|
|
int32_t entity_temperatures[SMU75_NUM_GPU_TES];
|
|
int32_t initial_entity_temperatures[SMU75_NUM_GPU_TES];
|
|
int32_t Limit;
|
|
int32_t Hyst;
|
|
int32_t therm_influence_coeff_table[SMU75_DTE_ITERATIONS * SMU75_DTE_SOURCES * SMU75_DTE_SINKS * 2];
|
|
int32_t therm_node_table[SMU75_DTE_ITERATIONS * SMU75_DTE_SOURCES * SMU75_DTE_SINKS];
|
|
uint16_t ConfigTDPPowerScalar;
|
|
uint16_t FanSpeedPowerScalar;
|
|
uint16_t OverDrivePowerScalar;
|
|
uint16_t OverDriveLimitScalar;
|
|
uint16_t FinalPowerScalar;
|
|
uint8_t VariantID;
|
|
uint8_t spare997;
|
|
|
|
SMU7_HystController_Data HystControllerData;
|
|
|
|
int32_t temperature_gradient_slope;
|
|
int32_t temperature_gradient;
|
|
uint32_t measured_temperature;
|
|
};
|
|
|
|
|
|
typedef struct SMU7_BapmScoreboard SMU7_BapmScoreboard;
|
|
|
|
struct SMU7_AcpiScoreboard {
|
|
uint32_t SavedInterruptMask[2];
|
|
uint8_t LastACPIRequest;
|
|
uint8_t CgBifResp;
|
|
uint8_t RequestType;
|
|
uint8_t Padding;
|
|
SMU75_Discrete_ACPILevel D0Level;
|
|
};
|
|
|
|
typedef struct SMU7_AcpiScoreboard SMU7_AcpiScoreboard;
|
|
|
|
struct SMU75_Discrete_PmFuses {
|
|
uint8_t BapmVddCVidHiSidd[8];
|
|
|
|
uint8_t BapmVddCVidLoSidd[8];
|
|
|
|
uint8_t VddCVid[8];
|
|
|
|
uint8_t SviLoadLineEn;
|
|
uint8_t SviLoadLineVddC;
|
|
uint8_t SviLoadLineTrimVddC;
|
|
uint8_t SviLoadLineOffsetVddC;
|
|
|
|
uint16_t TDC_VDDC_PkgLimit;
|
|
uint8_t TDC_VDDC_ThrottleReleaseLimitPerc;
|
|
uint8_t TDC_MAWt;
|
|
|
|
uint8_t TdcWaterfallCtl;
|
|
uint8_t LPMLTemperatureMin;
|
|
uint8_t LPMLTemperatureMax;
|
|
uint8_t Reserved;
|
|
|
|
uint8_t LPMLTemperatureScaler[16];
|
|
|
|
int16_t FuzzyFan_ErrorSetDelta;
|
|
int16_t FuzzyFan_ErrorRateSetDelta;
|
|
int16_t FuzzyFan_PwmSetDelta;
|
|
uint16_t Reserved6;
|
|
|
|
uint8_t GnbLPML[16];
|
|
|
|
uint8_t GnbLPMLMaxVid;
|
|
uint8_t GnbLPMLMinVid;
|
|
uint8_t Reserved1[2];
|
|
|
|
uint16_t BapmVddCBaseLeakageHiSidd;
|
|
uint16_t BapmVddCBaseLeakageLoSidd;
|
|
|
|
uint16_t VFT_Temp[3];
|
|
uint8_t Version;
|
|
uint8_t padding;
|
|
|
|
SMU_QuadraticCoeffs VFT_ATE[3];
|
|
|
|
SMU_QuadraticCoeffs AVFS_GB;
|
|
SMU_QuadraticCoeffs ATE_ACBTC_GB;
|
|
|
|
SMU_QuadraticCoeffs P2V;
|
|
|
|
uint32_t PsmCharzFreq;
|
|
|
|
uint16_t InversionVoltage;
|
|
uint16_t PsmCharzTemp;
|
|
|
|
uint32_t EnabledAvfsModules;
|
|
|
|
SMU_QuadraticCoeffs BtcGbv_CksOff;
|
|
};
|
|
|
|
typedef struct SMU75_Discrete_PmFuses SMU75_Discrete_PmFuses;
|
|
|
|
struct SMU7_Discrete_Log_Header_Table {
|
|
uint32_t version;
|
|
uint32_t asic_id;
|
|
uint16_t flags;
|
|
uint16_t entry_size;
|
|
uint32_t total_size;
|
|
uint32_t num_of_entries;
|
|
uint8_t type;
|
|
uint8_t mode;
|
|
uint8_t filler_0[2];
|
|
uint32_t filler_1[2];
|
|
};
|
|
|
|
typedef struct SMU7_Discrete_Log_Header_Table SMU7_Discrete_Log_Header_Table;
|
|
|
|
struct SMU7_Discrete_Log_Cntl {
|
|
uint8_t Enabled;
|
|
uint8_t Type;
|
|
uint8_t padding[2];
|
|
uint32_t BufferSize;
|
|
uint32_t SamplesLogged;
|
|
uint32_t SampleSize;
|
|
uint32_t AddrL;
|
|
uint32_t AddrH;
|
|
};
|
|
|
|
typedef struct SMU7_Discrete_Log_Cntl SMU7_Discrete_Log_Cntl;
|
|
|
|
#if defined SMU__DGPU_ONLY
|
|
#define CAC_ACC_NW_NUM_OF_SIGNALS 87
|
|
#endif
|
|
|
|
|
|
struct SMU7_Discrete_Cac_Collection_Table {
|
|
uint32_t temperature;
|
|
uint32_t cac_acc_nw[CAC_ACC_NW_NUM_OF_SIGNALS];
|
|
};
|
|
|
|
typedef struct SMU7_Discrete_Cac_Collection_Table SMU7_Discrete_Cac_Collection_Table;
|
|
|
|
struct SMU7_Discrete_Cac_Verification_Table {
|
|
uint32_t VddcTotalPower;
|
|
uint32_t VddcLeakagePower;
|
|
uint32_t VddcConstantPower;
|
|
uint32_t VddcGfxDynamicPower;
|
|
uint32_t VddcUvdDynamicPower;
|
|
uint32_t VddcVceDynamicPower;
|
|
uint32_t VddcAcpDynamicPower;
|
|
uint32_t VddcPcieDynamicPower;
|
|
uint32_t VddcDceDynamicPower;
|
|
uint32_t VddcCurrent;
|
|
uint32_t VddcVoltage;
|
|
uint32_t VddciTotalPower;
|
|
uint32_t VddciLeakagePower;
|
|
uint32_t VddciConstantPower;
|
|
uint32_t VddciDynamicPower;
|
|
uint32_t Vddr1TotalPower;
|
|
uint32_t Vddr1LeakagePower;
|
|
uint32_t Vddr1ConstantPower;
|
|
uint32_t Vddr1DynamicPower;
|
|
uint32_t spare[4];
|
|
uint32_t temperature;
|
|
};
|
|
|
|
typedef struct SMU7_Discrete_Cac_Verification_Table SMU7_Discrete_Cac_Verification_Table;
|
|
|
|
struct SMU7_Discrete_Pm_Status_Table {
|
|
int32_t T_meas_max[SMU75_THERMAL_INPUT_LOOP_COUNT];
|
|
int32_t T_meas_acc[SMU75_THERMAL_INPUT_LOOP_COUNT];
|
|
|
|
uint32_t I_calc_max;
|
|
uint32_t I_calc_acc;
|
|
uint32_t P_meas_acc;
|
|
uint32_t V_meas_load_acc;
|
|
uint32_t I_meas_acc;
|
|
uint32_t P_meas_acc_vddci;
|
|
uint32_t V_meas_load_acc_vddci;
|
|
uint32_t I_meas_acc_vddci;
|
|
|
|
uint16_t Sclk_dpm_residency[8];
|
|
uint16_t Uvd_dpm_residency[8];
|
|
uint16_t Vce_dpm_residency[8];
|
|
uint16_t Mclk_dpm_residency[4];
|
|
|
|
uint32_t P_roc_acc;
|
|
uint32_t PkgPwr_max;
|
|
uint32_t PkgPwr_acc;
|
|
uint32_t MclkSwitchingTime_max;
|
|
uint32_t MclkSwitchingTime_acc;
|
|
uint32_t FanPwm_acc;
|
|
uint32_t FanRpm_acc;
|
|
uint32_t Gfx_busy_acc;
|
|
uint32_t Mc_busy_acc;
|
|
uint32_t Fps_acc;
|
|
|
|
uint32_t AccCnt;
|
|
};
|
|
|
|
typedef struct SMU7_Discrete_Pm_Status_Table SMU7_Discrete_Pm_Status_Table;
|
|
|
|
struct SMU7_Discrete_AutoWattMan_Status_Table {
|
|
int32_t T_meas_acc[SMU75_THERMAL_INPUT_LOOP_COUNT];
|
|
uint16_t Sclk_dpm_residency[8];
|
|
uint16_t Mclk_dpm_residency[4];
|
|
uint32_t TgpPwr_acc;
|
|
uint32_t Gfx_busy_acc;
|
|
uint32_t Mc_busy_acc;
|
|
uint32_t AccCnt;
|
|
};
|
|
|
|
typedef struct SMU7_Discrete_AutoWattMan_Status_Table SMU7_Discrete_AutoWattMan_Status_Table;
|
|
|
|
#define SMU7_MAX_GFX_CU_COUNT 24
|
|
#define SMU7_MIN_GFX_CU_COUNT 8
|
|
#define SMU7_GFX_CU_PG_ENABLE_DC_MAX_CU_SHIFT 0
|
|
#define SMU7_GFX_CU_PG_ENABLE_DC_MAX_CU_MASK (0xFFFF << SMU7_GFX_CU_PG_ENABLE_DC_MAX_CU_SHIFT)
|
|
#define SMU7_GFX_CU_PG_ENABLE_AC_MAX_CU_SHIFT 16
|
|
#define SMU7_GFX_CU_PG_ENABLE_AC_MAX_CU_MASK (0xFFFF << SMU7_GFX_CU_PG_ENABLE_AC_MAX_CU_SHIFT)
|
|
|
|
struct SMU7_GfxCuPgScoreboard {
|
|
uint8_t Enabled;
|
|
uint8_t WaterfallUp;
|
|
uint8_t WaterfallDown;
|
|
uint8_t WaterfallLimit;
|
|
uint8_t CurrMaxCu;
|
|
uint8_t TargMaxCu;
|
|
uint8_t ClampMode;
|
|
uint8_t Active;
|
|
uint8_t MaxSupportedCu;
|
|
uint8_t MinSupportedCu;
|
|
uint8_t PendingGfxCuHostInterrupt;
|
|
uint8_t LastFilteredMaxCuInteger;
|
|
uint16_t FilteredMaxCu;
|
|
uint16_t FilteredMaxCuAlpha;
|
|
uint16_t FilterResetCount;
|
|
uint16_t FilterResetCountLimit;
|
|
uint8_t ForceCu;
|
|
uint8_t ForceCuCount;
|
|
uint8_t AcModeMaxCu;
|
|
uint8_t DcModeMaxCu;
|
|
};
|
|
|
|
typedef struct SMU7_GfxCuPgScoreboard SMU7_GfxCuPgScoreboard;
|
|
|
|
#define SMU7_SCLK_CAC 0x561
|
|
#define SMU7_MCLK_CAC 0xF9
|
|
#define SMU7_VCLK_CAC 0x2DE
|
|
#define SMU7_DCLK_CAC 0x2DE
|
|
#define SMU7_ECLK_CAC 0x25E
|
|
#define SMU7_ACLK_CAC 0x25E
|
|
#define SMU7_SAMCLK_CAC 0x25E
|
|
#define SMU7_DISPCLK_CAC 0x100
|
|
#define SMU7_CAC_CONSTANT 0x2EE3430
|
|
#define SMU7_CAC_CONSTANT_SHIFT 18
|
|
|
|
#define SMU7_VDDCI_MCLK_CONST 1765
|
|
#define SMU7_VDDCI_MCLK_CONST_SHIFT 16
|
|
#define SMU7_VDDCI_VDDCI_CONST 50958
|
|
#define SMU7_VDDCI_VDDCI_CONST_SHIFT 14
|
|
#define SMU7_VDDCI_CONST 11781
|
|
#define SMU7_VDDCI_STROBE_PWR 1331
|
|
|
|
#define SMU7_VDDR1_CONST 693
|
|
#define SMU7_VDDR1_CAC_WEIGHT 20
|
|
#define SMU7_VDDR1_CAC_WEIGHT_SHIFT 19
|
|
#define SMU7_VDDR1_STROBE_PWR 512
|
|
|
|
#define SMU7_AREA_COEFF_UVD 0xA78
|
|
#define SMU7_AREA_COEFF_VCE 0x190A
|
|
#define SMU7_AREA_COEFF_ACP 0x22D1
|
|
#define SMU7_AREA_COEFF_SAMU 0x534
|
|
|
|
#define SMU7_THERM_OUT_MODE_DISABLE 0x0
|
|
#define SMU7_THERM_OUT_MODE_THERM_ONLY 0x1
|
|
#define SMU7_THERM_OUT_MODE_THERM_VRHOT 0x2
|
|
|
|
#define SQ_Enable_MASK 0x1
|
|
#define SQ_IR_MASK 0x2
|
|
#define SQ_PCC_MASK 0x4
|
|
#define SQ_EDC_MASK 0x8
|
|
|
|
#define TCP_Enable_MASK 0x100
|
|
#define TCP_IR_MASK 0x200
|
|
#define TCP_PCC_MASK 0x400
|
|
#define TCP_EDC_MASK 0x800
|
|
|
|
#define TD_Enable_MASK 0x10000
|
|
#define TD_IR_MASK 0x20000
|
|
#define TD_PCC_MASK 0x40000
|
|
#define TD_EDC_MASK 0x80000
|
|
|
|
#define DB_Enable_MASK 0x1000000
|
|
#define DB_IR_MASK 0x2000000
|
|
#define DB_PCC_MASK 0x4000000
|
|
#define DB_EDC_MASK 0x8000000
|
|
|
|
#define SQ_Enable_SHIFT 0
|
|
#define SQ_IR_SHIFT 1
|
|
#define SQ_PCC_SHIFT 2
|
|
#define SQ_EDC_SHIFT 3
|
|
|
|
#define TCP_Enable_SHIFT 8
|
|
#define TCP_IR_SHIFT 9
|
|
#define TCP_PCC_SHIFT 10
|
|
#define TCP_EDC_SHIFT 11
|
|
|
|
#define TD_Enable_SHIFT 16
|
|
#define TD_IR_SHIFT 17
|
|
#define TD_PCC_SHIFT 18
|
|
#define TD_EDC_SHIFT 19
|
|
|
|
#define DB_Enable_SHIFT 24
|
|
#define DB_IR_SHIFT 25
|
|
#define DB_PCC_SHIFT 26
|
|
#define DB_EDC_SHIFT 27
|
|
|
|
#define PMFUSES_AVFSSIZE 104
|
|
|
|
#define BTCGB0_Vdroop_Enable_MASK 0x1
|
|
#define BTCGB1_Vdroop_Enable_MASK 0x2
|
|
#define AVFSGB0_Vdroop_Enable_MASK 0x4
|
|
#define AVFSGB1_Vdroop_Enable_MASK 0x8
|
|
|
|
#define BTCGB0_Vdroop_Enable_SHIFT 0
|
|
#define BTCGB1_Vdroop_Enable_SHIFT 1
|
|
#define AVFSGB0_Vdroop_Enable_SHIFT 2
|
|
#define AVFSGB1_Vdroop_Enable_SHIFT 3
|
|
|
|
#pragma pack(pop)
|
|
|
|
|
|
#endif
|
|
|