1e3dc1d862
GSC is a graphics system controller, it provides a chassis controller for graphics discrete cards. There are two MEI interfaces in GSC: HECI1 and HECI2. Both interfaces are on the BAR0 at offsets 0x00258000 and 0x00259000. GSC is a GT Engine (class 4: instance 6). HECI1 interrupt is signaled via bit 15 and HECI2 via bit 14 in the interrupt register. This patch exports GSC as auxiliary device for mei driver to bind to for HECI2 interface and prepares for HECI1 interface as it will follow up soon. CC: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Tomas Winkler <tomas.winkler@intel.com> Signed-off-by: Vitaly Lubart <vitaly.lubart@intel.com> Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com> Acked-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220419193314.526966-2-daniele.ceraolospurio@intel.com
37 lines
920 B
C
37 lines
920 B
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright(c) 2019-2022, Intel Corporation. All rights reserved.
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*/
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#ifndef __INTEL_GSC_DEV_H__
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#define __INTEL_GSC_DEV_H__
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#include <linux/types.h>
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struct drm_i915_private;
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struct intel_gt;
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struct mei_aux_device;
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#define INTEL_GSC_NUM_INTERFACES 2
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/*
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* The HECI1 bit corresponds to bit15 and HECI2 to bit14.
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* The reason for this is to allow growth for more interfaces in the future.
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*/
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#define GSC_IRQ_INTF(_x) BIT(15 - (_x))
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/**
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* struct intel_gsc - graphics security controller
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* @intf : gsc interface
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*/
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struct intel_gsc {
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struct intel_gsc_intf {
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struct mei_aux_device *adev;
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int irq;
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unsigned int id;
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} intf[INTEL_GSC_NUM_INTERFACES];
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};
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void intel_gsc_init(struct intel_gsc *gsc, struct drm_i915_private *dev_priv);
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void intel_gsc_fini(struct intel_gsc *gsc);
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void intel_gsc_irq_handler(struct intel_gt *gt, u32 iir);
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#endif /* __INTEL_GSC_DEV_H__ */
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