6694482a70
From testing on sc7180-trogdor devices, reading the GMU registers
needs the GMU clocks to be enabled. Those clocks get turned on in
a6xx_gmu_resume(). Confusingly enough, that function is called as a
result of the runtime_pm of the GPU "struct device", not the GMU
"struct device". Unfortunately the current a6xx_gpu_busy() grabs a
reference to the GMU's "struct device".
The fact that we were grabbing the wrong reference was easily seen to
cause crashes that happen if we change the GPU's pm_runtime usage to
not use autosuspend. It's also believed to cause some long tail GPU
crashes even with autosuspend.
We could look at changing it so that we do pm_runtime_get_if_in_use()
on the GPU's "struct device", but then we run into a different
problem. pm_runtime_get_if_in_use() will return 0 for the GPU's
"struct device" the whole time when we're in the "autosuspend
delay". That is, when we drop the last reference to the GPU but we're
waiting a period before actually suspending then we'll think the GPU
is off. One reason that's bad is that if the GPU didn't actually turn
off then the cycle counter doesn't lose state and that throws off all
of our calculations.
Let's change the code to keep track of the suspend state of
devfreq. msm_devfreq_suspend() is always called before we actually
suspend the GPU and msm_devfreq_resume() after we resume it. This
means we can use the suspended state to know if we're powered or not.
NOTE: one might wonder when exactly our status function is called when
devfreq is supposed to be disabled. The stack crawl I captured was:
msm_devfreq_get_dev_status
devfreq_simple_ondemand_func
devfreq_update_target
qos_notifier_call
qos_max_notifier_call
blocking_notifier_call_chain
pm_qos_update_target
freq_qos_apply
apply_constraint
__dev_pm_qos_update_request
dev_pm_qos_update_request
msm_devfreq_idle_work
Fixes: eadf79286a ("drm/msm: Check for powered down HW in the devfreq callbacks")
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Patchwork: https://patchwork.freedesktop.org/patch/489124/
Link: https://lore.kernel.org/r/20220610124639.v4.1.Ie846c5352bc307ee4248d7cab998ab3016b85d06@changeid
Signed-off-by: Rob Clark <robdclark@chromium.org>
90 lines
2.2 KiB
C
90 lines
2.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) 2017, 2019 The Linux Foundation. All rights reserved. */
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#ifndef __A6XX_GPU_H__
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#define __A6XX_GPU_H__
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#include "adreno_gpu.h"
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#include "a6xx.xml.h"
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#include "a6xx_gmu.h"
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extern bool hang_debug;
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struct a6xx_gpu {
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struct adreno_gpu base;
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struct drm_gem_object *sqe_bo;
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uint64_t sqe_iova;
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struct msm_ringbuffer *cur_ring;
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struct a6xx_gmu gmu;
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struct drm_gem_object *shadow_bo;
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uint64_t shadow_iova;
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uint32_t *shadow;
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bool has_whereami;
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void __iomem *llc_mmio;
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void *llc_slice;
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void *htw_llc_slice;
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bool have_mmu500;
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};
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#define to_a6xx_gpu(x) container_of(x, struct a6xx_gpu, base)
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/*
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* Given a register and a count, return a value to program into
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* REG_CP_PROTECT_REG(n) - this will block both reads and writes for _len
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* registers starting at _reg.
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*/
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#define A6XX_PROTECT_NORDWR(_reg, _len) \
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((1 << 31) | \
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(((_len) & 0x3FFF) << 18) | ((_reg) & 0x3FFFF))
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/*
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* Same as above, but allow reads over the range. For areas of mixed use (such
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* as performance counters) this allows us to protect a much larger range with a
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* single register
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*/
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#define A6XX_PROTECT_RDONLY(_reg, _len) \
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((((_len) & 0x3FFF) << 18) | ((_reg) & 0x3FFFF))
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static inline bool a6xx_has_gbif(struct adreno_gpu *gpu)
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{
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if(adreno_is_a630(gpu))
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return false;
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return true;
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}
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#define shadowptr(_a6xx_gpu, _ring) ((_a6xx_gpu)->shadow_iova + \
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((_ring)->id * sizeof(uint32_t)))
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int a6xx_gmu_resume(struct a6xx_gpu *gpu);
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int a6xx_gmu_stop(struct a6xx_gpu *gpu);
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int a6xx_gmu_wait_for_idle(struct a6xx_gmu *gmu);
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bool a6xx_gmu_isidle(struct a6xx_gmu *gmu);
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int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state);
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void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state);
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int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node);
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void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu);
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void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp,
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bool suspended);
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unsigned long a6xx_gmu_get_freq(struct msm_gpu *gpu);
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void a6xx_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
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struct drm_printer *p);
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struct msm_gpu_state *a6xx_gpu_state_get(struct msm_gpu *gpu);
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int a6xx_gpu_state_put(struct msm_gpu_state *state);
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#endif /* __A6XX_GPU_H__ */
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