57cbdbe65e
Originally it was assumed based on Nvidia's open-gpu-docs and testing that
NVDisplay required that at least one wndw which belongs to a given head to
be used as the controlling channel
(NVC37D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL) in order for CRC capture
to function. While this is the case on Volta, Turing actually adds the
ability to instead use the core channel as the controlling channel. For
Turing this is quite useful, as it means that we can always default to the
core channel as the controlling channel and we don't need to be concerned
about ensuring we have at least one wndw channel owned by a head with CRC
output enabled. While Volta lacks this ability, Volta conveniently also
lacks flexible wndw mapping - meaning that we can always rely on each head
having four wndw channels mapped to it regardless of the atomic state.
So, simply use the hard-coded wndw mappings we're guaranteed to have on
Volta as the controlling channel, and use the core channel as the
controlling channel for Turing+. As a result this also renders the plane
ownership logic in nv50_crc_atomic_check() unnessecary, which gives us one
less thing to implement when we get support for flexible wndw mapping. We
also can entirely drop the wndw parameter from our set_src callbacks, and
the atomic state.
v2 (Karol): put prackets around complex macro definition
removed spaces before :32 in structs
Cc: Martin Peres <martin.peres@free.fr>
Cc: Jeremy Cline <jcline@redhat.com>
Cc: Simon Ser <contact@emersion.fr>
Signed-off-by: Lyude Paul <lyude@redhat.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Link: https://gitlab.freedesktop.org/drm/nouveau/-/merge_requests/10
131 lines
3.8 KiB
C
131 lines
3.8 KiB
C
/* SPDX-License-Identifier: MIT */
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#ifndef __NV50_CRC_H__
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#define __NV50_CRC_H__
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#include <linux/mutex.h>
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#include <drm/drm_crtc.h>
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#include <drm/drm_vblank_work.h>
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#include <nvif/mem.h>
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#include <nvkm/subdev/bios.h>
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#include "nouveau_encoder.h"
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struct nv50_atom;
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struct nv50_disp;
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struct nv50_head;
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#if IS_ENABLED(CONFIG_DEBUG_FS)
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enum nv50_crc_source {
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NV50_CRC_SOURCE_NONE = 0,
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NV50_CRC_SOURCE_AUTO,
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NV50_CRC_SOURCE_RG,
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NV50_CRC_SOURCE_OUTP_ACTIVE,
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NV50_CRC_SOURCE_OUTP_COMPLETE,
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NV50_CRC_SOURCE_OUTP_INACTIVE,
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};
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/* RG -> SF (DP only)
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* -> SOR
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* -> PIOR
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* -> DAC
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*/
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enum nv50_crc_source_type {
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NV50_CRC_SOURCE_TYPE_NONE = 0,
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NV50_CRC_SOURCE_TYPE_SOR,
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NV50_CRC_SOURCE_TYPE_PIOR,
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NV50_CRC_SOURCE_TYPE_DAC,
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NV50_CRC_SOURCE_TYPE_RG,
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NV50_CRC_SOURCE_TYPE_SF,
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};
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struct nv50_crc_notifier_ctx {
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struct nvif_mem mem;
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struct nvif_object ntfy;
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};
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struct nv50_crc_atom {
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enum nv50_crc_source src;
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};
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struct nv50_crc_func {
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int (*set_src)(struct nv50_head *, int or, enum nv50_crc_source_type type,
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struct nv50_crc_notifier_ctx *ctx);
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int (*set_ctx)(struct nv50_head *, struct nv50_crc_notifier_ctx *);
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u32 (*get_entry)(struct nv50_head *, struct nv50_crc_notifier_ctx *,
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enum nv50_crc_source, int idx);
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bool (*ctx_finished)(struct nv50_head *,
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struct nv50_crc_notifier_ctx *);
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short flip_threshold;
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short num_entries;
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size_t notifier_len;
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};
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struct nv50_crc {
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spinlock_t lock;
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struct nv50_crc_notifier_ctx ctx[2];
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struct drm_vblank_work flip_work;
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enum nv50_crc_source src;
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u64 frame;
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short entry_idx;
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short flip_threshold;
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u8 ctx_idx : 1;
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bool ctx_changed : 1;
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};
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void nv50_crc_init(struct drm_device *dev);
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int nv50_head_crc_late_register(struct nv50_head *);
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void nv50_crc_handle_vblank(struct nv50_head *head);
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int nv50_crc_verify_source(struct drm_crtc *, const char *, size_t *);
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const char *const *nv50_crc_get_sources(struct drm_crtc *, size_t *);
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int nv50_crc_set_source(struct drm_crtc *, const char *);
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int nv50_crc_atomic_check_head(struct nv50_head *, struct nv50_head_atom *,
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struct nv50_head_atom *);
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void nv50_crc_atomic_check_outp(struct nv50_atom *atom);
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void nv50_crc_atomic_stop_reporting(struct drm_atomic_state *);
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void nv50_crc_atomic_init_notifier_contexts(struct drm_atomic_state *);
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void nv50_crc_atomic_release_notifier_contexts(struct drm_atomic_state *);
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void nv50_crc_atomic_start_reporting(struct drm_atomic_state *);
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void nv50_crc_atomic_set(struct nv50_head *, struct nv50_head_atom *);
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void nv50_crc_atomic_clr(struct nv50_head *);
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extern const struct nv50_crc_func crc907d;
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extern const struct nv50_crc_func crcc37d;
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extern const struct nv50_crc_func crcc57d;
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#else /* IS_ENABLED(CONFIG_DEBUG_FS) */
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struct nv50_crc {};
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struct nv50_crc_func {};
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struct nv50_crc_atom {};
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#define nv50_crc_verify_source NULL
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#define nv50_crc_get_sources NULL
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#define nv50_crc_set_source NULL
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static inline void nv50_crc_init(struct drm_device *dev) {}
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static inline int
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nv50_head_crc_late_register(struct nv50_head *head) { return 0; }
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static inline void nv50_crc_handle_vblank(struct nv50_head *head) {}
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static inline int
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nv50_crc_atomic_check_head(struct nv50_head *head,
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struct nv50_head_atom *asyh,
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struct nv50_head_atom *armh) { return 0; }
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static inline void nv50_crc_atomic_check_outp(struct nv50_atom *atom) {}
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static inline void
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nv50_crc_atomic_stop_reporting(struct drm_atomic_state *state) {}
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static inline void
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nv50_crc_atomic_init_notifier_contexts(struct drm_atomic_state *state) {}
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static inline void
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nv50_crc_atomic_release_notifier_contexts(struct drm_atomic_state *state) {}
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static inline void
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nv50_crc_atomic_start_reporting(struct drm_atomic_state *state) {}
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static inline void
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nv50_crc_atomic_set(struct nv50_head *head, struct nv50_head_atom *state) {}
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static inline void
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nv50_crc_atomic_clr(struct nv50_head *head) {}
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#endif /* IS_ENABLED(CONFIG_DEBUG_FS) */
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#endif /* !__NV50_CRC_H__ */
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