781eef5b34
This improves performance by allowing the scheduler to move the tx scheduling work to idle CPUs. Since tx scheduling work is very latency sensitive and kept short via AQL, sched_set_fifo_low is used to keep worker priority above normal tasks Signed-off-by: Felix Fietkau <nbd@nbd.name>
65 lines
1.7 KiB
C
65 lines
1.7 KiB
C
/* SPDX-License-Identifier: ISC */
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/*
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* Copyright (C) 2018 Lorenzo Bianconi <lorenzo.bianconi83@gmail.com>
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*/
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#ifndef __MT76x02_DMA_H
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#define __MT76x02_DMA_H
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#include "mt76x02.h"
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#include "dma.h"
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#define MT_TXD_INFO_LEN GENMASK(15, 0)
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#define MT_TXD_INFO_NEXT_VLD BIT(16)
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#define MT_TXD_INFO_TX_BURST BIT(17)
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#define MT_TXD_INFO_80211 BIT(19)
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#define MT_TXD_INFO_TSO BIT(20)
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#define MT_TXD_INFO_CSO BIT(21)
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#define MT_TXD_INFO_WIV BIT(24)
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#define MT_TXD_INFO_QSEL GENMASK(26, 25)
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#define MT_TXD_INFO_DPORT GENMASK(29, 27)
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#define MT_TXD_INFO_TYPE GENMASK(31, 30)
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#define MT_RX_FCE_INFO_LEN GENMASK(13, 0)
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#define MT_RX_FCE_INFO_SELF_GEN BIT(15)
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#define MT_RX_FCE_INFO_CMD_SEQ GENMASK(19, 16)
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#define MT_RX_FCE_INFO_EVT_TYPE GENMASK(23, 20)
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#define MT_RX_FCE_INFO_PCIE_INTR BIT(24)
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#define MT_RX_FCE_INFO_QSEL GENMASK(26, 25)
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#define MT_RX_FCE_INFO_D_PORT GENMASK(29, 27)
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#define MT_RX_FCE_INFO_TYPE GENMASK(31, 30)
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/* MCU request message header */
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#define MT_MCU_MSG_LEN GENMASK(15, 0)
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#define MT_MCU_MSG_CMD_SEQ GENMASK(19, 16)
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#define MT_MCU_MSG_CMD_TYPE GENMASK(26, 20)
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#define MT_MCU_MSG_PORT GENMASK(29, 27)
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#define MT_MCU_MSG_TYPE GENMASK(31, 30)
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#define MT_MCU_MSG_TYPE_CMD BIT(30)
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#define MT_RX_HEADROOM 32
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#define MT76X02_RX_RING_SIZE 256
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enum dma_msg_port {
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WLAN_PORT,
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CPU_RX_PORT,
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CPU_TX_PORT,
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HOST_PORT,
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VIRTUAL_CPU_RX_PORT,
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VIRTUAL_CPU_TX_PORT,
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DISCARD,
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};
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static inline bool
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mt76x02_wait_for_wpdma(struct mt76_dev *dev, int timeout)
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{
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return __mt76_poll(dev, MT_WPDMA_GLO_CFG,
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MT_WPDMA_GLO_CFG_TX_DMA_BUSY |
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MT_WPDMA_GLO_CFG_RX_DMA_BUSY,
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0, timeout);
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}
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int mt76x02_dma_init(struct mt76x02_dev *dev);
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void mt76x02_dma_disable(struct mt76x02_dev *dev);
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#endif /* __MT76x02_DMA_H */
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