b3e29075b2
Define handlers specific to cAVS 1.5 platforms, that is SKL, KBL, AML and all other variants based on this very version of AudioDSP architecture. Most are specific to SKL-alike platforms with only skl_log_buffer_offset() being exposed and used later by younger equivalents. Signed-off-by: Amadeusz Sławiński <amadeuszx.slawinski@linux.intel.com> Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com> Link: https://lore.kernel.org/r/20220516101116.190192-15-cezary.rojewski@intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
125 lines
3.3 KiB
C
125 lines
3.3 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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//
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// Copyright(c) 2021-2022 Intel Corporation. All rights reserved.
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//
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// Authors: Cezary Rojewski <cezary.rojewski@intel.com>
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// Amadeusz Slawinski <amadeuszx.slawinski@linux.intel.com>
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//
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#include <linux/devcoredump.h>
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#include <linux/slab.h>
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#include <sound/hdaudio_ext.h>
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#include "avs.h"
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#include "messages.h"
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static int skl_enable_logs(struct avs_dev *adev, enum avs_log_enable enable, u32 aging_period,
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u32 fifo_full_period, unsigned long resource_mask, u32 *priorities)
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{
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struct skl_log_state_info *info;
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u32 size, num_cores = adev->hw_cfg.dsp_cores;
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int ret, i;
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if (fls_long(resource_mask) > num_cores)
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return -EINVAL;
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size = struct_size(info, logs_core, num_cores);
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info = kzalloc(size, GFP_KERNEL);
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if (!info)
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return -ENOMEM;
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info->core_mask = resource_mask;
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if (enable)
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for_each_set_bit(i, &resource_mask, GENMASK(num_cores, 0)) {
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info->logs_core[i].enable = enable;
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info->logs_core[i].min_priority = *priorities++;
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}
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else
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for_each_set_bit(i, &resource_mask, GENMASK(num_cores, 0))
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info->logs_core[i].enable = enable;
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ret = avs_ipc_set_enable_logs(adev, (u8 *)info, size);
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kfree(info);
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if (ret)
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return AVS_IPC_RET(ret);
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return 0;
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}
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int skl_log_buffer_offset(struct avs_dev *adev, u32 core)
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{
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return core * avs_log_buffer_size(adev);
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}
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/* fw DbgLogWp registers */
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#define FW_REGS_DBG_LOG_WP(core) (0x30 + 0x4 * core)
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static int
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skl_log_buffer_status(struct avs_dev *adev, union avs_notify_msg *msg)
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{
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unsigned long flags;
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void __iomem *buf;
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u16 size, write, offset;
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spin_lock_irqsave(&adev->dbg.trace_lock, flags);
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if (!kfifo_initialized(&adev->dbg.trace_fifo)) {
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spin_unlock_irqrestore(&adev->dbg.trace_lock, flags);
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return 0;
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}
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size = avs_log_buffer_size(adev) / 2;
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write = readl(avs_sram_addr(adev, AVS_FW_REGS_WINDOW) + FW_REGS_DBG_LOG_WP(msg->log.core));
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/* determine buffer half */
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offset = (write < size) ? size : 0;
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/* Address is guaranteed to exist in SRAM2. */
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buf = avs_log_buffer_addr(adev, msg->log.core) + offset;
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__kfifo_fromio_locked(&adev->dbg.trace_fifo, buf, size, &adev->dbg.fifo_lock);
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wake_up(&adev->dbg.trace_waitq);
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spin_unlock_irqrestore(&adev->dbg.trace_lock, flags);
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return 0;
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}
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static int skl_coredump(struct avs_dev *adev, union avs_notify_msg *msg)
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{
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u8 *dump;
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dump = vzalloc(AVS_FW_REGS_SIZE);
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if (!dump)
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return -ENOMEM;
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memcpy_fromio(dump, avs_sram_addr(adev, AVS_FW_REGS_WINDOW), AVS_FW_REGS_SIZE);
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dev_coredumpv(adev->dev, dump, AVS_FW_REGS_SIZE, GFP_KERNEL);
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return 0;
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}
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static bool
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skl_d0ix_toggle(struct avs_dev *adev, struct avs_ipc_msg *tx, bool wake)
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{
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/* unsupported on cAVS 1.5 hw */
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return false;
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}
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static int skl_set_d0ix(struct avs_dev *adev, bool enable)
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{
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/* unsupported on cAVS 1.5 hw */
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return 0;
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}
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const struct avs_dsp_ops skl_dsp_ops = {
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.power = avs_dsp_core_power,
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.reset = avs_dsp_core_reset,
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.stall = avs_dsp_core_stall,
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.irq_handler = avs_dsp_irq_handler,
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.irq_thread = avs_dsp_irq_thread,
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.int_control = avs_dsp_interrupt_control,
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.load_basefw = avs_cldma_load_basefw,
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.load_lib = avs_cldma_load_library,
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.transfer_mods = avs_cldma_transfer_modules,
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.enable_logs = skl_enable_logs,
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.log_buffer_offset = skl_log_buffer_offset,
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.log_buffer_status = skl_log_buffer_status,
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.coredump = skl_coredump,
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.d0ix_toggle = skl_d0ix_toggle,
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.set_d0ix = skl_set_d0ix,
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};
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