4b3f7644ae
To pick the changes from:d6d0c7f681("x86/cpufeatures: Add PerfMonV2 feature bit")296d5a17e7("KVM: SEV-ES: Use V_TSC_AUX if available instead of RDTSC/MSR_TSC_AUX intercepts")f30903394e("x86/cpufeatures: Add virtual TSC_AUX feature bit")8ad7e8f696("x86/fpu/xsave: Support XSAVEC in the kernel")59bd54a84d("x86/tdx: Detect running as a TDX guest in early boot")a77d41ac3a("x86/cpufeatures: Add AMD Fam19h Branch Sampling feature") This only causes these perf files to be rebuilt: CC /tmp/build/perf/bench/mem-memcpy-x86-64-asm.o CC /tmp/build/perf/bench/mem-memset-x86-64-asm.o And addresses this perf build warning: Warning: Kernel ABI header at 'tools/arch/x86/include/asm/cpufeatures.h' differs from latest version at 'arch/x86/include/asm/cpufeatures.h' diff -u tools/arch/x86/include/asm/cpufeatures.h arch/x86/include/asm/cpufeatures.h Warning: Kernel ABI header at 'tools/arch/x86/include/asm/disabled-features.h' differs from latest version at 'arch/x86/include/asm/disabled-features.h' diff -u tools/arch/x86/include/asm/disabled-features.h arch/x86/include/asm/disabled-features.h Cc: Peter Zijlstra <peterz@infradead.org> Cc: Sandipan Das <sandipan.das@amd.com> Cc: Babu Moger <babu.moger@amd.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Dave Hansen <dave.hansen@linux.intel.com> Cc: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> Cc: Stephane Eranian <eranian@google.com> Cc: Peter Zijlstra <peterz@infradead.org> Link: https://lore.kernel.org/lkml/YrDkgmwhLv+nKeOo@kernel.org Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
97 lines
2.6 KiB
C
97 lines
2.6 KiB
C
#ifndef _ASM_X86_DISABLED_FEATURES_H
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#define _ASM_X86_DISABLED_FEATURES_H
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/* These features, although they might be available in a CPU
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* will not be used because the compile options to support
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* them are not present.
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*
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* This code allows them to be checked and disabled at
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* compile time without an explicit #ifdef. Use
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* cpu_feature_enabled().
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*/
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#ifdef CONFIG_X86_UMIP
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# define DISABLE_UMIP 0
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#else
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# define DISABLE_UMIP (1<<(X86_FEATURE_UMIP & 31))
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#endif
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#ifdef CONFIG_X86_64
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# define DISABLE_VME (1<<(X86_FEATURE_VME & 31))
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# define DISABLE_K6_MTRR (1<<(X86_FEATURE_K6_MTRR & 31))
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# define DISABLE_CYRIX_ARR (1<<(X86_FEATURE_CYRIX_ARR & 31))
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# define DISABLE_CENTAUR_MCR (1<<(X86_FEATURE_CENTAUR_MCR & 31))
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# define DISABLE_PCID 0
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#else
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# define DISABLE_VME 0
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# define DISABLE_K6_MTRR 0
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# define DISABLE_CYRIX_ARR 0
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# define DISABLE_CENTAUR_MCR 0
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# define DISABLE_PCID (1<<(X86_FEATURE_PCID & 31))
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#endif /* CONFIG_X86_64 */
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#ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
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# define DISABLE_PKU 0
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# define DISABLE_OSPKE 0
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#else
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# define DISABLE_PKU (1<<(X86_FEATURE_PKU & 31))
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# define DISABLE_OSPKE (1<<(X86_FEATURE_OSPKE & 31))
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#endif /* CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS */
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#ifdef CONFIG_X86_5LEVEL
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# define DISABLE_LA57 0
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#else
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# define DISABLE_LA57 (1<<(X86_FEATURE_LA57 & 31))
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#endif
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#ifdef CONFIG_PAGE_TABLE_ISOLATION
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# define DISABLE_PTI 0
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#else
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# define DISABLE_PTI (1 << (X86_FEATURE_PTI & 31))
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#endif
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#ifdef CONFIG_INTEL_IOMMU_SVM
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# define DISABLE_ENQCMD 0
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#else
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# define DISABLE_ENQCMD (1 << (X86_FEATURE_ENQCMD & 31))
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#endif
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#ifdef CONFIG_X86_SGX
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# define DISABLE_SGX 0
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#else
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# define DISABLE_SGX (1 << (X86_FEATURE_SGX & 31))
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#endif
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#ifdef CONFIG_INTEL_TDX_GUEST
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# define DISABLE_TDX_GUEST 0
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#else
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# define DISABLE_TDX_GUEST (1 << (X86_FEATURE_TDX_GUEST & 31))
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#endif
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/*
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* Make sure to add features to the correct mask
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*/
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#define DISABLED_MASK0 (DISABLE_VME)
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#define DISABLED_MASK1 0
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#define DISABLED_MASK2 0
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#define DISABLED_MASK3 (DISABLE_CYRIX_ARR|DISABLE_CENTAUR_MCR|DISABLE_K6_MTRR)
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#define DISABLED_MASK4 (DISABLE_PCID)
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#define DISABLED_MASK5 0
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#define DISABLED_MASK6 0
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#define DISABLED_MASK7 (DISABLE_PTI)
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#define DISABLED_MASK8 (DISABLE_TDX_GUEST)
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#define DISABLED_MASK9 (DISABLE_SGX)
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#define DISABLED_MASK10 0
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#define DISABLED_MASK11 0
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#define DISABLED_MASK12 0
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#define DISABLED_MASK13 0
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#define DISABLED_MASK14 0
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#define DISABLED_MASK15 0
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#define DISABLED_MASK16 (DISABLE_PKU|DISABLE_OSPKE|DISABLE_LA57|DISABLE_UMIP| \
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DISABLE_ENQCMD)
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#define DISABLED_MASK17 0
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#define DISABLED_MASK18 0
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#define DISABLED_MASK19 0
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#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 20)
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#endif /* _ASM_X86_DISABLED_FEATURES_H */
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