Ganesan Ramalingam d66f3f0e10 MIPS: Add MSI support for XLP9XX ... In XLP9XX, the interrupt routing table for MSI-X has been moved to the PCIe controller's config space from PIC. There are also 32 MSI-X interrupts available per link on XLP9XX. Update XLP MSI/MSI-X code to handle this. Signed-off-by: Ganesan Ramalingam <ganesanr@broadcom.com> Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: g@linux-mips.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6912/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>		2014-05-30 16:51:02 +02:00
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bridge.h	MIPS: Netlogic: XLP9XX bridge and DRAM code	2014-01-24 22:39:49 +01:00
cpucontrol.h	MIPS: Netlogic: Split XLP L1 i-cache among threads	2013-02-17 00:15:20 +01:00
iomap.h	MIPS: Netlogic: PIC freq calculation for XLP 9XX/2XX	2014-05-30 16:49:41 +02:00
pcibus.h	MIPS: Add MSI support for XLP9XX	2014-05-30 16:51:02 +02:00
pic.h	MIPS: Add MSI support for XLP9XX	2014-05-30 16:51:02 +02:00
sys.h	MIPS: Netlogic: Update XLP9XX/2XX core freq calculation	2014-05-30 16:50:13 +02:00
uart.h	MIPS: Netlogic: XLP9XX UART offset	2014-01-24 22:39:48 +01:00
xlp.h	MIPS: Add MSI support for XLP9XX	2014-05-30 16:51:02 +02:00