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fix fixed src main ram dma timings being off by 1

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This commit is contained in:
Jaklyy 2024-12-23 19:31:45 -05:00
parent 8d94384907
commit 01ba503373
1 changed files with 4 additions and 4 deletions
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8
src/NDS.cpp
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@ -1115,12 +1115,12 @@ void NDS::MainRAMHandleARM9()
if (burststart == 2 || dma->SrcAddrInc <= 0)
{
A9ContentionTS += ARM9MemTimings[srcaddr>>14][6] + ((burststart == 2) && (ARM9MemTimings[srcaddr>>14][6] == 1));
MainRAMTimestamp += ARM9MemTimings[srcaddr>>14][6] + ((burststart == 2) && (ARM9MemTimings[srcaddr>>14][6] == 1));
MainRAMTimestamp += ARM9MemTimings[srcaddr>>14][6] - 1 + ((burststart == 2) && (ARM9MemTimings[srcaddr>>14][6] == 1));
}
else
{
A9ContentionTS += ARM9MemTimings[srcaddr>>14][7];
MainRAMTimestamp += ARM9MemTimings[srcaddr>>14][7];
MainRAMTimestamp += ARM9MemTimings[srcaddr>>14][7] - 1;
}
DMALastWasMainRAM = false;
}
@ -1221,12 +1221,12 @@ void NDS::MainRAMHandleARM9()
if (burststart == 2 || dma->SrcAddrInc <= 0)
{
A9ContentionTS += ARM9MemTimings[srcaddr>>14][4] + ((burststart == 2) && (ARM9MemTimings[srcaddr>>14][4] == 1));
MainRAMTimestamp += ARM9MemTimings[srcaddr>>14][4] + ((burststart == 2) && (ARM9MemTimings[srcaddr>>14][4] == 1));
MainRAMTimestamp += ARM9MemTimings[srcaddr>>14][4] - 1 + ((burststart == 2) && (ARM9MemTimings[srcaddr>>14][4] == 1));
}
else
{
A9ContentionTS += ARM9MemTimings[srcaddr>>14][5];
MainRAMTimestamp += ARM9MemTimings[srcaddr>>14][5];
MainRAMTimestamp += ARM9MemTimings[srcaddr>>14][5] - 1;
}
DMALastWasMainRAM = false;
}