diff --git a/src/ARM.cpp b/src/ARM.cpp
index b9c7379e..9aa84503 100644
--- a/src/ARM.cpp
+++ b/src/ARM.cpp
@@ -1513,7 +1513,6 @@ void ARMv5::ForceInterlock_2()
 
 void ARMv5::QueueFunction(void (ARMv5::*QueueEntry)(void))
 {
-    if (QueueEntry == nullptr) return;
     if ((NDS.ARM9Timestamp >= NDS.ARM9Target) || (MRTrack.Type != MainRAMType::Null))
         FuncQueue[FuncQueueFill++] = QueueEntry;
     else
diff --git a/src/CP15.cpp b/src/CP15.cpp
index c7cea83a..14e9bc53 100644
--- a/src/CP15.cpp
+++ b/src/CP15.cpp
@@ -443,7 +443,7 @@ bool ARMv5::ICacheLookup(const u32 addr)
             Store = false;
 
             RetVal = cacheLine[(addr & (ICACHE_LINELENGTH -1)) / 4];
-            QueueFunction(DelayedQueue);
+            if (DelayedQueue != nullptr) QueueFunction(DelayedQueue);
             return true;
         }
     }
@@ -556,7 +556,7 @@ void ARMv5::ICacheLookup_2()
     }
     Store = false;
     DataRegion = Mem9_Null;
-    QueueFunction(DelayedQueue);
+    if (DelayedQueue != nullptr) QueueFunction(DelayedQueue);
 }
 
 void ARMv5::ICacheInvalidateByAddr(const u32 addr)