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StapleButter 2017-02-01 00:31:23 +01:00
parent 1f5faf8291
commit 6d2092a106
2 changed files with 5 additions and 5 deletions
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4
ARM_InstrTable.h
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@ -75,8 +75,8 @@ INSTRFUNC_PROTO(ARMInstrTable[4096]) =
// 0000 1001 0000 // 0000 1001 0000
A_ADD_REG_LSL_IMM_S, A_ADD_REG_LSL_REG_S, A_ADD_REG_LSR_IMM_S, A_ADD_REG_LSR_REG_S, A_ADD_REG_LSL_IMM_S, A_ADD_REG_LSL_REG_S, A_ADD_REG_LSR_IMM_S, A_ADD_REG_LSR_REG_S,
A_ADD_REG_ASR_IMM_S, A_ADD_REG_ASR_REG_S, A_ADD_REG_ROR_IMM_S, A_ADD_REG_ROR_REG_S, A_ADD_REG_ASR_IMM_S, A_ADD_REG_ASR_REG_S, A_ADD_REG_ROR_IMM_S, A_ADD_REG_ROR_REG_S,
A_UNK, A_UMULL, A_UNK, A_LDRH_POST_REG, A_ADD_REG_LSL_IMM_S, A_UMULL, A_ADD_REG_LSR_IMM_S, A_LDRH_POST_REG,
A_UNK, A_LDRSB_POST_REG, A_UNK, A_LDRSH_POST_REG, A_ADD_REG_ASR_IMM_S, A_LDRSB_POST_REG, A_ADD_REG_ROR_IMM_S, A_LDRSH_POST_REG,
// 0000 1010 0000 // 0000 1010 0000
A_ADC_REG_LSL_IMM, A_ADC_REG_LSL_REG, A_ADC_REG_LSR_IMM, A_ADC_REG_LSR_REG, A_ADC_REG_LSL_IMM, A_ADC_REG_LSL_REG, A_ADC_REG_LSR_IMM, A_ADC_REG_LSR_REG,

6
melonDS.depend
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@ -10,7 +10,7 @@
1481161027 c:\documents\sources\melonds\types.h 1481161027 c:\documents\sources\melonds\types.h
1485901668 source:c:\documents\sources\melonds\nds.cpp 1485905010 source:c:\documents\sources\melonds\nds.cpp
<stdio.h> <stdio.h>
<string.h> <string.h>
"NDS.h" "NDS.h"
@ -35,7 +35,7 @@
"NDS.h" "NDS.h"
"CP15.h" "CP15.h"
1485883199 c:\documents\sources\melonds\arm_instrtable.h 1485905451 c:\documents\sources\melonds\arm_instrtable.h
1485795549 c:\documents\sources\melonds\arminterpreter.h 1485795549 c:\documents\sources\melonds\arminterpreter.h
"types.h" "types.h"
@ -80,7 +80,7 @@
1485900740 c:\documents\sources\melonds\spi.h 1485900740 c:\documents\sources\melonds\spi.h
1485901732 source:c:\documents\sources\melonds\spi.cpp 1485905004 source:c:\documents\sources\melonds\spi.cpp
<stdio.h> <stdio.h>
<string.h> <string.h>
"NDS.h" "NDS.h"