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put out some fires

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This commit is contained in:
Jaklyy 2024-12-26 18:22:42 -05:00
parent cec4c2c880
commit c9e7eec2b5
5 changed files with 13 additions and 26 deletions
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7
src/ARM.cpp
View file

@ -896,6 +896,7 @@ void ARMv5::Execute()
{
while (FuncQueueActive)
{
//printf("A9: A:%i, F:%i, P:%i, E:%i, I:%08llX, N:%08llX, 7:%08llX 15:%08X\n", FuncQueueActive, FuncQueueFill, FuncQueueProg, FuncQueueEnd, CurInstr, NextInstr[0], NDS.ARM7.CurInstr, R[15]);
(this->*FuncQueue[FuncQueueProg])();
if (FuncQueueFill == FuncQueueProg)
@ -938,7 +939,7 @@ void ARMv5::Execute()
if constexpr (mode == CPUExecuteMode::InterpreterGDB)
GdbCheckC(); // gdb might throw a hissy fit about this change but idc
//printf("A9: A:%i, F:%i, P:%i, E:%i, I:%08llX, P:%08X, 15:%08X\n", FuncQueueActive, FuncQueueFill, FuncQueueProg, FuncQueueEnd, CurInstr, PC, R[15]);
//printf("A9: A:%i, F:%i, P:%i, E:%i, I:%08llX, N:%08llX, 7:%08llX 15:%08X\n", FuncQueueActive, FuncQueueFill, FuncQueueProg, FuncQueueEnd, CurInstr, NextInstr[0], NDS.ARM7.CurInstr, R[15]);
(this->*FuncQueue[FuncQueueProg])();
if (FuncQueueFill > 0) // check if we started the queue up
@ -1098,6 +1099,7 @@ void ARMv4::Execute()
{
while (FuncQueueActive)
{
//printf("A7: A:%i, F:%i, P:%i, E:%i, I:%08llX, N:%08llX 15:%08X\n", FuncQueueActive, FuncQueueFill, FuncQueueProg, FuncQueueEnd, CurInstr, NextInstr[0], R[15]);
(this->*FuncQueue[FuncQueueProg])();
if (FuncQueueFill == FuncQueueProg)
@ -1139,7 +1141,7 @@ void ARMv4::Execute()
if constexpr (mode == CPUExecuteMode::InterpreterGDB)
GdbCheckC();
//printf("A7: A:%i, F:%i, P:%i, E:%i, I:%08llX, 15:%08X\n", FuncQueueActive, FuncQueueFill, FuncQueueProg, FuncQueueEnd, CurInstr, R[15]);
//printf("A7: A:%i, F:%i, P:%i, E:%i, I:%08llX, N:%08llX 15:%08X\n", FuncQueueActive, FuncQueueFill, FuncQueueProg, FuncQueueEnd, CurInstr, NextInstr[0], R[15]);
(this->*FuncQueue[FuncQueueProg])();
if (FuncQueueFill > 0) // check if we started the queue up
@ -1511,6 +1513,7 @@ void ARMv5::ForceInterlock_2()
void ARMv5::QueueFunction(void (ARMv5::*QueueEntry)(void))
{
if (QueueEntry == nullptr) return;
if ((NDS.ARM9Timestamp >= NDS.ARM9Target) || (MRTrack.Type != MainRAMType::Null))
FuncQueue[FuncQueueFill++] = QueueEntry;
else

4
src/ARM.h
View file

@ -250,10 +250,6 @@ public:
u16 STRRegs;
u32 FetchAddr[17];
u32 STRVal[16];
// debugging crud: REMOVE ME
u8 abt;
u64 iter;
u64 IRQTimestamp;

21
src/ARMInterpreter.cpp
View file

@ -262,15 +262,11 @@ void A_MRS(ARM* cpu)
void A_MCR(ARM* cpu)
{
if (cpu->CheckInterlock)
{
if (!((cpu->CPSR & 0x1F) == 0x10)) ((ARMv5*)cpu)->HandleInterlocksExecute<false>((cpu->CurInstr>>12)&0xF);
return;
}
if ((cpu->CPSR & 0x1F) == 0x10)
return A_UNK(cpu);
if (cpu->CheckInterlock) return ((ARMv5*)cpu)->HandleInterlocksExecute<false>((cpu->CurInstr>>12)&0xF);
u32 cp = (cpu->CurInstr >> 8) & 0xF;
u32 op = (cpu->CurInstr >> 21) & 0x7;
u32 cn = (cpu->CurInstr >> 16) & 0xF;
@ -281,7 +277,7 @@ void A_MCR(ARM* cpu)
if (cpu->Num==0 && cp==15)
{
((ARMv5*)cpu)->CP15Write((cn<<8)|(cm<<4)|cpinfo|(op<<12), val); // TODO: IF THIS RAISES AN EXCEPTION WE DO A DOUBLE CODE FETCH; FIX THAT
((ARMv5*)cpu)->CP15Write((cn<<8)|(cm<<4)|cpinfo|(op<<12), val);
}
else if (cpu->Num==1 && cp==14)
{
@ -293,22 +289,17 @@ void A_MCR(ARM* cpu)
return A_UNK(cpu); // TODO: check what kind of exception it really is
}
// TODO: SINCE THIS DOES A CODE FETCH WE NEED TO DELAY ANY MPU UPDATES UNTIL *AFTER* THE CODE FETCH
if (cpu->Num==0) cpu->AddCycles_CI(5); // checkme
else /* ARM7 */ cpu->AddCycles_CI(1 + 1); // TODO: checkme
}
void A_MRC(ARM* cpu)
{
if (cpu->CheckInterlock)
{
if (!((cpu->CPSR & 0x1F) == 0x10)) ((ARMv5*)cpu)->HandleInterlocksExecute<false>((cpu->CurInstr>>12)&0xF);
return;
}
if ((cpu->CPSR & 0x1F) == 0x10)
return A_UNK(cpu);
if (cpu->CheckInterlock) return ((ARMv5*)cpu)->HandleInterlocksExecute<false>((cpu->CurInstr>>12)&0xF);
u32 cp = (cpu->CurInstr >> 8) & 0xF;
u32 op = (cpu->CurInstr >> 21) & 0x7;
u32 cn = (cpu->CurInstr >> 16) & 0xF;
@ -322,7 +313,7 @@ void A_MRC(ARM* cpu)
else
{
// r15 updates the top 4 bits of the cpsr, done to "allow for conditional branching based on coprocessor status"
u32 flags = ((ARMv5*)cpu)->CP15Read((cn<<8)|(cm<<4)|cpinfo|(op<<12)) & 0xF0000000; // TODO: IF THIS RAISES AN EXCEPTION WE DO A DOUBLE CODE FETCH; FIX THAT
u32 flags = ((ARMv5*)cpu)->CP15Read((cn<<8)|(cm<<4)|cpinfo|(op<<12)) & 0xF0000000;
cpu->CPSR = (cpu->CPSR & ~0xF0000000) | flags;
}
}

6
src/ARMInterpreter_LoadStore.cpp
View file

@ -27,11 +27,7 @@ namespace melonDS::ARMInterpreter
template <bool bitfield>
inline bool ExecuteStage(ARM* cpu, u16 ilmask)
{
if (cpu->Num == 0)
{
if (cpu->CheckInterlock) { ((ARMv5*)cpu)->HandleInterlocksExecute<bitfield>(ilmask); return false;}
((ARMv5*)cpu)->AddCycles_C();
}
if (cpu->CheckInterlock) { ((ARMv5*)cpu)->HandleInterlocksExecute<bitfield>(ilmask); return false;}
return true;
}

1
src/CP15.cpp
View file

@ -1808,6 +1808,7 @@ void ARMv5::CP15Write(u32 id, u32 val)
// if it wasn't cached yet, it will be loaded into cache
// low bits are set to 0x1C to trick cache streaming
CP15Queue = val;
DelayedQueue = nullptr;
QueueFunction(&ARMv5::ICachePrefetch_2);
return;