diff --git a/src/CP15.cpp b/src/CP15.cpp index 14e9bc53..6afca641 100644 --- a/src/CP15.cpp +++ b/src/CP15.cpp @@ -330,29 +330,10 @@ void ARMv5::UpdateRegionTimings(u32 addrstart, u32 addrend) { u8* bustimings = NDS.ARM9MemTimings[i]; - if (NDS.ARM9ClockShift == 1) - { - MemTimings[i][0] = (bustimings[0] << NDS.ARM9ClockShift) - 1; - MemTimings[i][1] = (bustimings[2] << NDS.ARM9ClockShift) - 1; - MemTimings[i][2] = bustimings[3] << NDS.ARM9ClockShift; // sequentials technically should probably be -1 as well? - // but it doesn't really matter as long as i also dont force align the start of sequential accesses, now does it? - } - else - { - if (NDS.ARM9Regions[i] != Mem9_MainRAM) - { - // 133MHz clock has 1 less bus cycle penalty on ns accesses - MemTimings[i][0] = ((bustimings[0] - 1) << NDS.ARM9ClockShift) - 1; - MemTimings[i][1] = ((bustimings[2] - 1) << NDS.ARM9ClockShift) - 1; - } - else - { - // we handle the different timings for main ram in the read/write functions (they're slightly more complicated...) - MemTimings[i][0] = (bustimings[0] << NDS.ARM9ClockShift) - 1; - MemTimings[i][1] = (bustimings[2] << NDS.ARM9ClockShift) - 1; - } - MemTimings[i][2] = bustimings[3] << NDS.ARM9ClockShift; - } + MemTimings[i][0] = (bustimings[0] << NDS.ARM9ClockShift) - 1; + MemTimings[i][1] = (bustimings[2] << NDS.ARM9ClockShift) - 1; + MemTimings[i][2] = (bustimings[3] << NDS.ARM9ClockShift) - 1; // sequentials technically should probably be -1 as well? + // but it doesn't really matter as long as i also dont force align the start of sequential accesses, now does it? } } @@ -532,13 +513,15 @@ void ARMv5::ICacheLookup_2() // Wait until the entire cache line is filled before continuing with execution if (CP15BISTTestStateRegister & CP15_BIST_TR_DISABLE_ICACHE_STREAMING) [[unlikely]] { - NDS.ARM9Timestamp += MemTimings[tag >> 14][1] + (MemTimings[tag >> 14][2] * ((DCACHE_LINELENGTH / 4) - 1)); + u32 stall = (4 - NDS.ARM9ClockShift) << NDS.ARM9ClockShift; + NDS.ARM9Timestamp += (MemTimings[tag >> 14][1] + stall) + ((MemTimings[tag >> 14][2] + 1) * ((DCACHE_LINELENGTH / 4) - 1)); if (NDS.ARM9Timestamp < TimestampMemory) NDS.ARM9Timestamp = TimestampMemory; // this should never trigger in practice } else // ICache Streaming logic { - u8 ns = MemTimings[addr>>14][1]; - u8 seq = MemTimings[addr>>14][2]; + u32 stall = (4 - NDS.ARM9ClockShift) << NDS.ARM9ClockShift; + u8 ns = MemTimings[addr>>14][1] + stall; + u8 seq = MemTimings[addr>>14][2] + 1; u8 linepos = (addr & 0x1F) / 4; // technically this is one too low, but we want that actually @@ -774,8 +757,10 @@ void ARMv5::DCacheLookup_3() { NDS.ARM9Timestamp = NDS.ARM9Timestamp + ((1<> 14][1] + (MemTimings[tag >> 14][2] * ((DCACHE_LINELENGTH / 4) - 1)); - DataCycles = MemTimings[tag>>14][2]; + u32 stall = (4 - NDS.ARM9ClockShift) << NDS.ARM9ClockShift; + + NDS.ARM9Timestamp += (MemTimings[tag >> 14][1] + stall) + ((MemTimings[tag >> 14][2] + 1) * ((DCACHE_LINELENGTH / 4) - 1)); + DataCycles = MemTimings[tag>>14][2] + 1; DataRegion = NDS.ARM9Regions[addr>>14]; if (((NDS.ARM9Timestamp <= WBReleaseTS) && (NDS.ARM9Regions[addr>>14] == WBLastRegion)) // check write buffer @@ -789,9 +774,10 @@ void ARMv5::DCacheLookup_3() NDS.ARM9Timestamp += 1<>14][1]; - u8 seq = MemTimings[addr>>14][2]; + + u32 stall = (4 - NDS.ARM9ClockShift) << NDS.ARM9ClockShift; + u8 ns = MemTimings[addr>>14][1] + stall; + u8 seq = MemTimings[addr>>14][2] + 1; u8 linepos = (addr & 0x1F) >> 2; // technically this is one too low, but we want that actually @@ -1194,7 +1180,7 @@ bool ARMv5::WriteBufferHandle() NDS.MainRAMTimestamp = NDS.A9ContentionTS + 9; NDS.MainRAMLastAccess = A9LAST; } - else cycles = (MemTimings[WBCurAddr>>14][0] - 5) >> NDS.ARM9ClockShift; // todo: twl timings + else cycles = NDS.ARM9MemTimings[WBCurAddr>>14][0]; // todo: twl timings break; } case 1: @@ -1208,7 +1194,7 @@ bool ARMv5::WriteBufferHandle() cycles = 3; NDS.MainRAMLastAccess = A9LAST; } - else cycles = (MemTimings[WBCurAddr>>14][0] - 5) >> NDS.ARM9ClockShift; // todo: twl timings + else cycles = NDS.ARM9MemTimings[WBCurAddr>>14][0]; // todo: twl timings break; } case 3: @@ -1226,7 +1212,7 @@ bool ARMv5::WriteBufferHandle() } else { - cycles = MemTimings[WBCurAddr>>14][2] >> NDS.ARM9ClockShift; + cycles = NDS.ARM9MemTimings[WBCurAddr>>14][3]; break; } } @@ -1241,7 +1227,7 @@ bool ARMv5::WriteBufferHandle() cycles = 4; NDS.MainRAMLastAccess = A9LAST; } - else cycles = (MemTimings[WBCurAddr>>14][1] - 5) >> NDS.ARM9ClockShift; // todo: twl timings + else cycles = NDS.ARM9MemTimings[WBCurAddr>>14][2]; // todo: twl timings break; } } @@ -2265,7 +2251,11 @@ void ARMv5::CodeRead32_4() { u32 addr = FetchAddr[16]; - if (NDS.ARM9Timestamp < NDS.DMA9Timestamp) NDS.ARM9Timestamp = NDS.DMA9Timestamp; + if (NDS.ARM9Timestamp < NDS.DMA9Timestamp) NDS.ARM9Timestamp = (NDS.DMA9Timestamp + ((1<> 14][1]; @@ -2276,8 +2266,6 @@ void ARMv5::CodeRead32_4() Store = false; DataRegion = Mem9_Null; - - RetVal = BusRead32(addr); QueueFunction(DelayedQueue); } @@ -2418,15 +2406,17 @@ void ARMv5::DRead8_5() u32 addr = FetchAddr[reg]; u32 dummy; u32* val = (LDRFailedRegs & (1<> 14][0]; DataCycles = 3<> 14][0]; DataCycles = 3<> 14][1]; DataCycles = 3<>14]; if ((NDS.ARM9Timestamp <= WBReleaseTS) && (DataRegion == WBLastRegion)) // check write buffer NDS.ARM9Timestamp += 1<> 24) == 0x02) { MRTrack.Type = MainRAMType::Fetch; @@ -2829,6 +2824,8 @@ void ARMv5::DRead32S_4() } else { + NDS.ARM9Timestamp = (NDS.ARM9Timestamp + ((1<>14]; if ((NDS.ARM9Timestamp <= WBReleaseTS) && (DataRegion == WBLastRegion)) // check write buffer NDS.ARM9Timestamp += 1<>14][2]; DataCycles = MemTimings[addr>>14][2]; @@ -2852,7 +2851,6 @@ void ARMv5::DRead32S_5A() if (WBTimestamp < ((NDS.ARM9Timestamp - (3<>14][1]; DataCycles = 3<> 14][0] + 1; + + BusWrite8(addr, val); + NDS.DMA9Timestamp = NDS.ARM9Timestamp -= 1; - NDS.DMA9Timestamp = NDS.ARM9Timestamp += MemTimings[addr >> 14][0]; DataCycles = 3<>14]; if (WBTimestamp < ((NDS.ARM9Timestamp + ((1<> 14][0] + 1; + + BusWrite16(addr, val); + NDS.DMA9Timestamp = NDS.ARM9Timestamp -= 1; - NDS.DMA9Timestamp = NDS.ARM9Timestamp += MemTimings[addr >> 14][0]; DataCycles = 3<>14]; if (WBTimestamp < ((NDS.ARM9Timestamp + ((1<> 14][1] + 1; + + BusWrite32(addr, val); + NDS.DMA9Timestamp = NDS.ARM9Timestamp -= 1; - NDS.DMA9Timestamp = NDS.ARM9Timestamp += MemTimings[addr >> 14][1]; DataCycles = 3<>14]; if (WBTimestamp < ((NDS.ARM9Timestamp + ((1<> 24) == 0x02) { MRTrack.Type = MainRAMType::Fetch; @@ -3398,6 +3405,7 @@ void ARMv5::DWrite32S_4() } else { + NDS.ARM9Timestamp = (NDS.ARM9Timestamp + ((1<>14][2] + 1; + + BusWrite32(addr, val); + + NDS.DMA9Timestamp = NDS.ARM9Timestamp -= 1; - NDS.DMA9Timestamp = NDS.ARM9Timestamp += MemTimings[addr>>14][2]; DataRegion = NDS.ARM9Regions[addr>>14]; if (WBTimestamp < ((NDS.ARM9Timestamp + ((1<>14][1] + 1; + + BusWrite32(addr, val); + + NDS.DMA9Timestamp = NDS.ARM9Timestamp -= 1; - NDS.DMA9Timestamp = NDS.ARM9Timestamp += MemTimings[addr>>14][1]; DataCycles = 3 << NDS.ARM9ClockShift; DataRegion = NDS.ARM9Regions[addr>>14]; if (WBTimestamp < ((NDS.ARM9Timestamp + ((1<> ARM9ClockShift) - TimerTimestamp[0]; + cycles = (std::max(ARM9Timestamp, DMA9Timestamp) >> ARM9ClockShift) - TimerTimestamp[0]; else cycles = ARM7Timestamp - TimerTimestamp[1];